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2. 发明专利

JP5226640B2 Semiconductor device and a method of manufacturing a semiconductor device 有权
公开(公告)号：JP5226640B2
公开(公告)日：2013-07-03
申请号：JP2009234821
申请日：2009-10-09
申请人：株式会社テラミクロス
发明人：宮本ツトム
IPC分类号： H01L23/12
CPC分类号： H01L2224/13

3. 发明专利

JP5138260B2 Chip-type electronic component 有权
公开(公告)号：JP5138260B2
公开(公告)日：2013-02-06
申请号：JP2007090453
申请日：2007-03-30
申请人：株式会社テラミクロス
发明人：由隆青木
IPC分类号： H01G4/40 , H01G4/12 , H01G4/33 , H01L21/822 , H01L27/04

4. 发明专利

JP2012204553A Semiconductor device manufacturing method and semiconductor device mounting structure manufacturing method 审中-公开
标题翻译：半导体器件制造方法和半导体器件安装结构制造方法
公开(公告)号：JP2012204553A
公开(公告)日：2012-10-22
申请号：JP2011066885
申请日：2011-03-25
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： ARAI KAZUYOSHI
IPC分类号： H01L23/12 , H01L21/60
CPC分类号： H01L2224/11 , H01L2924/07802 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve a lifetime of a bump by inhibiting bump fatigue.SOLUTION: A method comprises forming recesses 25b on a surface side of an encapsulation layer 25 of a semiconductor wafer 111 on which the encapsulation layer 25 is provided above one surface, and filling a low elastic material 26 having an elastic modulus lower than the elastic modulus of the encapsulation layer 25 in the recesses 25b to form bumps 27 above the one surface of the semiconductor wafer 111.
摘要翻译：要解决的问题：通过抑制凸起疲劳来提高凸块的寿命。解决方案：一种方法包括在半导体晶片111的封装层25的表面侧上形成凹部25b，在该半导体晶片111的一个表面上设置有封装层25，并填充弹性模量低于封装层25在凹部25b中的弹性模量，以在半导体晶片111的一个表面上方形成凸块27.版权所有：（C）2013，JPO＆INPIT

5. 发明专利

JP2012186403A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2012186403A
公开(公告)日：2012-09-27
申请号：JP2011049851
申请日：2011-03-08
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： SHIODA JUNJI
IPC分类号： H01L21/56 , H01L23/12
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can inhibit a dent from being formed on a surface of an encapsulation layer in a package.SOLUTION: In a semiconductor device manufacturing process, after forming an encapsulation film 17-1 in a temporary cured state by performing a series of processes including coating of a liquid encapsulation material 33 on a semiconductor wafer 21, defoaming and calcination, a series of processes including coating of the liquid encapsulation material 33, defoaming and final baking is performed again, and an encapsulation layer 17 forming an integrated layer without a borderline, which includes the encapsulation film 17-1 in the temporary cured state and an encapsulation film 17-2 composed of the encapsulation material 33 coated thereafter is formed. Accordingly, the encapsulation layer 17 having a uniform film thickness and a flat surface condition is formed.
摘要翻译：要解决的问题：提供一种能够抑制在封装中的封装层的表面上形成凹陷的半导体器件制造方法。解决方案：在半导体器件制造工艺中，在通过执行包括在半导体晶片21上涂覆液体封装材料33的一系列工艺，消泡和煅烧之后，在临时固化状态下形成封装膜17-1之后，再次进行包括液体包封材料33的涂布，消泡和最终烘烤的一系列处理，形成没有边界线的一体化层的封装层17，其包括处于临时固化状态的封装膜17-1和封装膜形成由其后涂覆的封装材料33构成的17-2。因此，形成具有均匀膜厚和平坦表面状态的封装层17。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP5033682B2 Semiconductor device and a method of manufacturing the same, and semiconductor device and a method of manufacturing the same that 有权
公开(公告)号：JP5033682B2
公开(公告)日：2012-09-26
申请号：JP2008062322
申请日：2008-03-12
申请人：株式会社テラミクロス
发明人：一郎三原 , 猛若林
IPC分类号： H01L23/12 , H01L25/065 , H01L25/07 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L25/105 , H01L2224/16
摘要： PROBLEM TO BE SOLVED: To make a structure in which wiring for connecting upper and lower layers is not provided in a semiconductor construction, in a semiconductor device in which a plurality of semiconductor constructions are laminated. SOLUTION: Since a solder ball 13b of a second semiconductor construction 1b is joined to a connection pad part of a lower layer wiring 22a of a first semiconductor construction 1a, the second semiconductor construction 1b is arranged under the first semiconductor construction 1a. In the side surface of the first and second semiconductor constructions 1a and 1b, side surface wirings 28a and 28b for connecting upper layer wirings 8a and 8b to lower layer wirings 22a and 22b are provided. In this case, since the side surface wirings 28a and 28b are provided only in the side surface of the first and second semiconductor constructions 1a and 1b, they prevent disconnection, even if the first and second semiconductor constructions 1a and 1b are twisted to some extent. COPYRIGHT: (C)2009,JPO&INPIT

7. 发明专利

JP2012174950A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012174950A
公开(公告)日：2012-09-10
申请号：JP2011036626
申请日：2011-02-23
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： KAWAMURA MASAO
IPC分类号： H01L23/12
CPC分类号： H01L2224/16
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a semiconductor structure called SOI, which is less likely to be restricted in circuit design to set a lower surface of a semiconductor substrate of the semiconductor structure to ground potential.SOLUTION: A semiconductor device comprises a multilayer printed board 12 and a semiconductor structure 31 called SOI mounted in a recess 15 provided on the side of a lower surface of the multilayer printed board 12 in a face-up manner. Further, the semiconductor structure 31 is mounted on a printed wiring board 1 by connection of a center part of a lower surface of a semiconductor substrate 33 with ground wiring 3 of the printed wiring board 1 via a conductive adhesive layer 43 arranged below the lower surface of the semiconductor substrate 33. In this case, it is almost unnecessary to regard a routing line for ground. Accordingly, it becomes possible to cause the semiconductor device to be less likely to be restricted in circuit design to set the lower surface of the semiconductor substrate 33 of the semiconductor structure 31 to ground potential.
摘要翻译：要解决的问题：提供一种包括称为SOI的半导体结构的半导体器件，其不太可能限制电路设计以将半导体结构的半导体衬底的下表面设置为接地电位。解决方案：半导体器件包括多层印刷电路板12和称为SOI的半导体结构31，其被安装在设置在多层印刷电路板12的下表面侧面上的凹部15中。此外，半导体结构31通过半导体衬底33的下表面的中心部分与印刷电路板1的接地布线3之间的连接，安装在印刷电路板1上，导电粘合层43布置在下表面在这种情况下，几乎不需要考虑用于地面的路线。因此，可以使半导体器件不太可能受到电路设计的限制，以将半导体结构31的半导体衬底33的下表面设置为接地电位。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP5004907B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP5004907B2
公开(公告)日：2012-08-22
申请号：JP2008225635
申请日：2008-09-03
申请人：株式会社テラミクロス
发明人：智宏伊藤
IPC分类号： H01L23/12 , H01L21/301
CPC分类号： H01L2224/11

9. 发明专利

JP2012074581A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012074581A
公开(公告)日：2012-04-12
申请号：JP2010218973
申请日：2010-09-29
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： KANEKO NORIHIKO
IPC分类号： H01L23/12 , H01L21/3205 , H01L23/52
CPC分类号： H01L24/97 , H01L24/82 , H01L2224/12105 , H01L2224/24 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/14 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To shorten the time required to form through holes without weakening the strength of a laser beam.SOLUTION: A semiconductor die 1 includes a semiconductor substrate 11, electric wiring 23 provided on the semiconductor substrate 11, and laser beam protection electrodes 27 provided on the electric wiring 23. A semiconductor device 40 includes the semiconductor die 1, a sealing layer 43 covering the semiconductor die 1 and having through holes 43a provided at a portion corresponding to the laser beam protection electrodes 27, and conductors 44 provided in the through holes 43a of the sealing layer 43. An upper surface of each laser beam protection electrode 27 has a first region 27d which contacts with the conductor 44 and a second region 27c which does not contact with the conductor 44.
摘要翻译：要解决的问题：缩短形成通孔所需的时间，而不会削弱激光束的强度。解决方案：半导体管芯1包括半导体衬底11，设置在半导体衬底11上的电线23和设置在电线23上的激光束保护电极27.半导体器件40包括半导体管芯1，密封层43覆盖半导体管芯1，并且具有设置在与激光束保护电极27相对应的部分的通孔43a，以及设置在密封层43的通孔43a中的导体44.每个激光束保护电极27的上表面具有与导体44接触的第一区域27d和不与导体44接触的第二区域27c。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP4913372B2 Semiconductor device 有权
公开(公告)号：JP4913372B2
公开(公告)日：2012-04-11
申请号：JP2005218290
申请日：2005-07-28
申请人：株式会社テラミクロス
发明人：修岡田
IPC分类号： H01L23/12
CPC分类号： H01L2224/18 , H01L2924/07811 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To set the bottom surface of an SOI substrate to a grounding potential in a semiconductor device wherein a semiconductor configuration having the SOI substrate is provided on a base plate. SOLUTION: The bottom surface of a silicon substrate 7 of an SOI substrate 6 of a semiconductor configuration 3 is connected via protruding electrodes 5 with a grounding layer 2 provided on the top surface of a base plate 1. The grounding layer 2 is connected with an upper-layer wiring 25 for grounding, via a continuity portion 32 interposed between the upper and lower sides of the semiconductor configuration 3 which is provided in a through-hole 31 provided in an upper-layer insulating film 22, an insulating layer 21, the grounding layer 2, and the base plate 1. Consequently, the bottom surface of the silicon substrate 7 of the SOI substrate 6 of the semiconductor configuration 3 is set to the grounding potential. COPYRIGHT: (C)2007,JPO&INPIT

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