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    • 1. 发明专利
    • Many-valued non-volatile semiconductor memory element and its manufacturing method
    • 多值非易失性半导体存储元件及其制造方法
    • JP2005340768A
    • 2005-12-08
    • JP2005030860
    • 2005-02-07
    • Asahi Glass Co LtdMitsumasa Koyanagi光正 小柳旭硝子株式会社
    • TAKADA MASAAKIKOYANAGI MITSUMASA
    • H01L21/316H01L21/8247H01L27/115H01L29/786H01L29/788H01L29/792
    • PROBLEM TO BE SOLVED: To provide a many-valued non-volatile semiconductor memory element which can perform a stable many-valued memory operation and can keep a sufficient memory window, and to provide its manufacturing method. SOLUTION: The structure is formed on a semiconductor substrate 1 and includes a source area 6, a drain area 7, a tunnel insulating layer 2 formed on a channel forming area, a charge holding layer 3 holding a charge introduced from a channel, an inter-gate insulating layer 4, and a control gate layer 5. The charge holding layer 3 is composed of ultra fine particles(work function is 4.2 eV or less) which are separately dispersed at a density of 10 12 -10 14 /cm 3 and function as a floating gate of a diameter of 5 nm or smaller, and a base insulator(an amorphous substance having an electronic affinity of 1.0 eV or less). COPYRIGHT: (C)2006,JPO&NCIPI
    • 要解决的问题:提供可以执行稳定的多值存储器操作并且可以保持足够的存储器窗口并提供其制造方法的多值非易失性半导体存储器元件。 解决方案:结构形成在半导体衬底1上,包括源极区6,漏极区7,形成在沟道形成区上的隧道绝缘层2,电荷保持层3,其保持从沟道引入的电荷 ,栅极间绝缘层4和控制栅极层5.电荷保持层3由以10 <12>的密度分开分散的超细颗粒(功函数为4.2eV以下) / SP> -10 14 / cm 3 ,并且用作直径为5nm以下的浮栅,以及基极绝缘体(具有电子亲和性的非晶体 1.0eV以下)。 版权所有(C)2006,JPO&NCIPI
    • 3. 发明专利
    • Nonvolatile semiconductor storage element and method for manufacturing the same
    • 非挥发性半导体存储元件及其制造方法
    • JP2005328029A
    • 2005-11-24
    • JP2005030859
    • 2005-02-07
    • Asahi Glass Co LtdMitsumasa Koyanagi光正 小柳旭硝子株式会社
    • TAKADA MASAAKIKOYANAGI MITSUMASA
    • B82B1/00H01L21/8247H01L27/115H01L29/788H01L29/792
    • PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage element contributing to improvement in the speed of data rewriting operation and the miniaturization and high density of the element, and to provide a method for manufacturing the nonvolatile semiconductor storage element. SOLUTION: The nonvolatile semiconductor storage element is provided with a source area 6 and a drain area 7 which are formed on a semiconductor substrate 1, a tunnel insulating layer 2 formed on a channel formation area, a charge holding layer 3 for holding charge injected from the channel, an inter-gate insulating layer 4, and a control gate 5. The charge holding layer 3 is constituted of ultrafine particulates (a work function is ≥4.2 eV) which are independently dispersed at the density of 10 12 to 10 14 particulates/cm 3 serving as floating gates having grain size of ≤5 nm, and a mother phase insulator (amorphous substance of which electron affinity is ≤1.0 eV). COPYRIGHT: (C)2006,JPO&NCIPI
    • 要解决的问题:提供一种有助于提高数据重写操作的速度和元件的小型化和高密度的非易失性半导体存储元件,并且提供一种用于制造非易失性半导体存储元件的方法。 解决方案:非易失性半导体存储元件设置有形成在半导体基板1上的源极区域6和漏极区域7,形成在沟道形成区域上的隧道绝缘层2,用于保持的电荷保持层3 从沟道注入的电荷,栅极间绝缘层4和控制栅极5.电荷保持层3由以10 12 至10 14 颗粒/ cm 3 / SP>作为具有≤5nm的晶粒尺寸的浮动栅极,以及母相绝缘体(其中电子 亲和力≤1.0eV)。 版权所有(C)2006,JPO&NCIPI
    • 4. 发明专利
    • Method of manufacturing integrated circuit device having three-dimensional lamination structure
    • 制造具有三维层叠结构的集成电路装置的方法
    • JP2012209596A
    • 2012-10-25
    • JP2012162142
    • 2012-07-20
    • Mitsumasa Koyanagi光正 小柳
    • KOYANAGI MITSUMASA
    • H01L25/065H01L21/60H01L25/07H01L25/18
    • H01L2224/16H01L2924/13091H01L2924/00
    • PROBLEM TO BE SOLVED: To provide a method of manufacturing an integrated circuit device with a three-dimensional lamination structure capable of arranging an electrical insulating adhesive agent in a clearance between semiconductor circuit layers with certainty, and of eliminating a need for removing a surplus adhesive agent overflowed from the clearance.SOLUTION: A plurality of embedded wires (conductive plugs) 15 are formed inside a first semiconductor circuit layer 1a, and their ends are exposed to a rear face of the first semiconductor circuit layer 1a. A plurality of bump electrodes 43a are formed on a surface of a second semiconductor circuit layer 2 so as to correspond to the respective plugs 15. An electrical insulating adhesive agent film 44a patterned in a shape not overlapped with the bump electrodes 43a is formed on the surface of the second semiconductor circuit layer 2. Thereafter, the rear face of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2 are opposed and approached to each other, and therebetween, at least a part of the respective bump electrodes 43a are compressed while deforming the adhesive agent film 44a to mechanically connect the embedded wires 15 and the bump electrodes 43a mutually and adhere both circuit layers 1a and 2 by the adhesive agent film 44a.
    • 要解决的问题:提供一种制造集成电路器件的方法,该集成电路器件具有能够确定地在半导体电路层之间的间隙中布置电绝缘粘合剂的三维层压结构,并且不需要去除 剩余的粘合剂从间隙溢出。 解决方案:在第一半导体电路层1a内部形成有多个嵌入导线(导电插塞)15,并且它们的端部暴露于第一半导体电路层1a的背面。 在第二半导体电路层2的表面上形成多个凸起电极43a,以便与各个插塞15相对应。形成与凸起电极43a不重叠的形状的电绝缘粘合剂膜44a形成在 此后,第一半导体电路层1a的背面和第二半导体电路层2的表面彼此相对并接近,并且在它们之间,至少部分各个凸起 电极43a在粘合剂膜44a变形的同时被压缩,以相互间接地连接嵌入线15和凸起电极43a,并且通过粘合剂膜44a粘附两个电路层1a和2。 版权所有(C)2013,JPO&INPIT
    • 5. 发明专利
    • Stacked semiconductor device with integrated sensor mounted thereon
    • 具有集成传感器的堆叠半导体器件
    • JP2007228460A
    • 2007-09-06
    • JP2006049605
    • 2006-02-27
    • Mitsumasa Koyanagi光正 小柳
    • KOYANAGI MITSUMASA
    • H01L27/146H04N5/335H04N5/353H04N5/369H04N5/374
    • H01L27/14603H01L27/14609H01L27/14623H01L27/14634H01L27/14636H01L27/14641H04N5/353H04N5/37457
    • PROBLEM TO BE SOLVED: To provide a sensor circuit and an addressing type image sensor for actualing high pixel aperture ratio while each signal charge of all pixels can be accumulated in a substantially simultaneous way. SOLUTION: Two or more pixels 11 arranged in matrix form are connected in parallel every n pieces at a common node 13 to form two or more pixel blocks 12. Each pixel block 12 includes n pieces of transfer gates TG 1 -TG n for opening and closing each path jointing n pieces of photoelectric transfer elements PD 1 -PD n connected in parallel at the common node 13, each photoelectric transfer element PD 1 -PD n , and the common node 13. As for each pixel block 12, a common reset transistor Tr RST for resetting the whole pixel 11 and a common amplifying transistor Tr AMP for amplifying signal read out from n pieces of pixels 11 are provided at external portion of the pixel block 12. COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供用于实现高像素孔径比的传感器电路和寻址型图像传感器,同时可以基本上同时地累积所有像素的每个信号电荷。 解决方案:以矩阵形式布置的两个或更多个像素11在公共节点13上每n个并行连接以形成两个或更多个像素块12.每个像素块12包括n个传送门TG <1> -TG n ,用于打开和关闭连接n个光电转移元件PD 1 -PD n 公共节点13,每个光电转移元件PD&lt; SB&gt; -PD&lt; SB&gt; n&gt;和公共节点13.对于每个像素块12,公共复位晶体管Tr 用于复位整个像素11的RST 和用于放大从n个像素11读出的信号的公共放大晶体管Tr AMP 被提供在像素块12的外部。 版权所有(C)2007,JPO&INPIT