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1. 发明专利

JP2005340768A Many-valued non-volatile semiconductor memory element and its manufacturing method 审中-公开
标题翻译：多值非易失性半导体存储元件及其制造方法
公开(公告)号：JP2005340768A
公开(公告)日：2005-12-08
申请号：JP2005030860
申请日：2005-02-07
申请人： Asahi Glass Co Ltd , Mitsumasa Koyanagi , 光正小柳 , 旭硝子株式会社
发明人： TAKADA MASAAKI , KOYANAGI MITSUMASA
IPC分类号： H01L21/316 , H01L21/8247 , H01L27/115 , H01L29/786 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a many-valued non-volatile semiconductor memory element which can perform a stable many-valued memory operation and can keep a sufficient memory window, and to provide its manufacturing method. SOLUTION: The structure is formed on a semiconductor substrate 1 and includes a source area 6, a drain area 7, a tunnel insulating layer 2 formed on a channel forming area, a charge holding layer 3 holding a charge introduced from a channel, an inter-gate insulating layer 4, and a control gate layer 5. The charge holding layer 3 is composed of ultra fine particles(work function is 4.2 eV or less) which are separately dispersed at a density of 10 12 -10 14 /cm 3 and function as a floating gate of a diameter of 5 nm or smaller, and a base insulator(an amorphous substance having an electronic affinity of 1.0 eV or less). COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以执行稳定的多值存储器操作并且可以保持足够的存储器窗口并提供其制造方法的多值非易失性半导体存储器元件。解决方案：结构形成在半导体衬底1上，包括源极区6，漏极区7，形成在沟道形成区上的隧道绝缘层2，电荷保持层3，其保持从沟道引入的电荷，栅极间绝缘层4和控制栅极层5.电荷保持层3由以10 <12>的密度分开分散的超细颗粒（功函数为4.2eV以下） / SP> -10 14 / cm 3 ，并且用作直径为5nm以下的浮栅，以及基极绝缘体（具有电子亲和性的非晶体 1.0eV以下）。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2007073775A Method for manufacturing integrated circuit device having three-dimensional laminated structure 有权
标题翻译：制造具有三维层叠结构的集成电路装置的方法
公开(公告)号：JP2007073775A
公开(公告)日：2007-03-22
申请号：JP2005259824
申请日：2005-09-07
申请人： Mitsumasa Koyanagi , 光正小柳
发明人： KOYANAGI MITSUMASA
IPC分类号： H01L21/60 , H01L21/3205 , H01L23/52
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L24/10 , H01L24/13 , H01L24/90 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13 , H01L2224/13147 , H01L2224/83192 , H01L2224/83194 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/18301 , H01L2924/19043 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit device having a three-dimensional laminated structure by which electrically insulating adhesive can be reliably arranged in gaps between semiconductor circuit layers and the necessity for removing excessive adhesive protruding from the gaps can be avoided. SOLUTION: Several buried interconnections (conductive plugs) 15 are formed in a first semiconductor circuit layer 1a, and their ends are exposed from the reverse side of the first semiconductor circuit layer 1a. Several bump electrodes 43a corresponding to the plugs 15 are formed on the surface of a second semiconductor circuit layer 2. An electrically insulating adhesive film 44a which is patterned in such a way that it does not overlap the bump electrodes 43a is formed on the surface of the second semiconductor circuit layer 2. After that, the buried interconnections 15 and the bump electrodes 43a are mechanically connected with one another by opposing the reverse side of the first semiconductor circuit layer 1a to the front surface of the second semiconductor circuit layer 2, bringing them closer to each other, and crushing at least a part of the bump electrodes 43a while the adhesive film 44a is deformed between the layers 1a and 2. At the same time, the circuit layers 1a and 2 are bonded by the adhesive film 44a. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种具有三维叠层结构的集成电路器件的制造方法，通过该方法可以将电绝缘性粘合剂可靠地布置在半导体电路层之间的间隙中，并且必须除去从可以避免间隙。解决方案：在第一半导体电路层1a中形成多个埋入互连（导电插塞）15，并且它们的端部从第一半导体电路层1a的背面露出。在第二半导体电路层2的表面上形成有与插头15相对应的多个凸起电极43a。以与突起电极43a不重叠的方式构图的电绝缘粘合膜44a形成在第二半导体电路层2.之后，通过将第一半导体电路层1a的反面与第二半导体电路层2的正面相对，将掩埋布线15和突起电极43a相互机械连接，使它们彼此更靠近，并且在粘合剂膜44a在层1a和2之间变形的同时破碎凸起电极43a的至少一部分。同时，电路层1a和2通过粘合膜44a粘合。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2005328029A Nonvolatile semiconductor storage element and method for manufacturing the same 审中-公开
标题翻译：非挥发性半导体存储元件及其制造方法
公开(公告)号：JP2005328029A
公开(公告)日：2005-11-24
申请号：JP2005030859
申请日：2005-02-07
申请人： Asahi Glass Co Ltd , Mitsumasa Koyanagi , 光正小柳 , 旭硝子株式会社
发明人： TAKADA MASAAKI , KOYANAGI MITSUMASA
IPC分类号： B82B1/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage element contributing to improvement in the speed of data rewriting operation and the miniaturization and high density of the element, and to provide a method for manufacturing the nonvolatile semiconductor storage element. SOLUTION: The nonvolatile semiconductor storage element is provided with a source area 6 and a drain area 7 which are formed on a semiconductor substrate 1, a tunnel insulating layer 2 formed on a channel formation area, a charge holding layer 3 for holding charge injected from the channel, an inter-gate insulating layer 4, and a control gate 5. The charge holding layer 3 is constituted of ultrafine particulates (a work function is ≥4.2 eV) which are independently dispersed at the density of 10 12 to 10 14 particulates/cm 3 serving as floating gates having grain size of ≤5 nm, and a mother phase insulator (amorphous substance of which electron affinity is ≤1.0 eV). COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种有助于提高数据重写操作的速度和元件的小型化和高密度的非易失性半导体存储元件，并且提供一种用于制造非易失性半导体存储元件的方法。解决方案：非易失性半导体存储元件设置有形成在半导体基板1上的源极区域6和漏极区域7，形成在沟道形成区域上的隧道绝缘层2，用于保持的电荷保持层3 从沟道注入的电荷，栅极间绝缘层4和控制栅极5.电荷保持层3由以10 12 至10 14 颗粒/ cm 3 / SP>作为具有≤5nm的晶粒尺寸的浮动栅极，以及母相绝缘体（其中电子亲和力≤1.0eV）。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2012209596A Method of manufacturing integrated circuit device having three-dimensional lamination structure 有权
标题翻译：制造具有三维层叠结构的集成电路装置的方法
公开(公告)号：JP2012209596A
公开(公告)日：2012-10-25
申请号：JP2012162142
申请日：2012-07-20
申请人： Mitsumasa Koyanagi , 光正小柳
发明人： KOYANAGI MITSUMASA
IPC分类号： H01L25/065 , H01L21/60 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an integrated circuit device with a three-dimensional lamination structure capable of arranging an electrical insulating adhesive agent in a clearance between semiconductor circuit layers with certainty, and of eliminating a need for removing a surplus adhesive agent overflowed from the clearance.SOLUTION: A plurality of embedded wires (conductive plugs) 15 are formed inside a first semiconductor circuit layer 1a, and their ends are exposed to a rear face of the first semiconductor circuit layer 1a. A plurality of bump electrodes 43a are formed on a surface of a second semiconductor circuit layer 2 so as to correspond to the respective plugs 15. An electrical insulating adhesive agent film 44a patterned in a shape not overlapped with the bump electrodes 43a is formed on the surface of the second semiconductor circuit layer 2. Thereafter, the rear face of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2 are opposed and approached to each other, and therebetween, at least a part of the respective bump electrodes 43a are compressed while deforming the adhesive agent film 44a to mechanically connect the embedded wires 15 and the bump electrodes 43a mutually and adhere both circuit layers 1a and 2 by the adhesive agent film 44a.
摘要翻译：要解决的问题：提供一种制造集成电路器件的方法，该集成电路器件具有能够确定地在半导体电路层之间的间隙中布置电绝缘粘合剂的三维层压结构，并且不需要去除剩余的粘合剂从间隙溢出。解决方案：在第一半导体电路层1a内部形成有多个嵌入导线（导电插塞）15，并且它们的端部暴露于第一半导体电路层1a的背面。在第二半导体电路层2的表面上形成多个凸起电极43a，以便与各个插塞15相对应。形成与凸起电极43a不重叠的形状的电绝缘粘合剂膜44a形成在此后，第一半导体电路层1a的背面和第二半导体电路层2的表面彼此相对并接近，并且在它们之间，至少部分各个凸起电极43a在粘合剂膜44a变形的同时被压缩，以相互间接地连接嵌入线15和凸起电极43a，并且通过粘合剂膜44a粘附两个电路层1a和2。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2007228460A Stacked semiconductor device with integrated sensor mounted thereon 审中-公开
标题翻译：具有集成传感器的堆叠半导体器件
公开(公告)号：JP2007228460A
公开(公告)日：2007-09-06
申请号：JP2006049605
申请日：2006-02-27
申请人： Mitsumasa Koyanagi , 光正小柳
发明人： KOYANAGI MITSUMASA
IPC分类号： H01L27/146 , H04N5/335 , H04N5/353 , H04N5/369 , H04N5/374
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14623 , H01L27/14634 , H01L27/14636 , H01L27/14641 , H04N5/353 , H04N5/37457
摘要： PROBLEM TO BE SOLVED: To provide a sensor circuit and an addressing type image sensor for actualing high pixel aperture ratio while each signal charge of all pixels can be accumulated in a substantially simultaneous way. SOLUTION: Two or more pixels 11 arranged in matrix form are connected in parallel every n pieces at a common node 13 to form two or more pixel blocks 12. Each pixel block 12 includes n pieces of transfer gates TG 1 -TG n for opening and closing each path jointing n pieces of photoelectric transfer elements PD 1 -PD n connected in parallel at the common node 13, each photoelectric transfer element PD 1 -PD n , and the common node 13. As for each pixel block 12, a common reset transistor Tr RST for resetting the whole pixel 11 and a common amplifying transistor Tr AMP for amplifying signal read out from n pieces of pixels 11 are provided at external portion of the pixel block 12. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供用于实现高像素孔径比的传感器电路和寻址型图像传感器，同时可以基本上同时地累积所有像素的每个信号电荷。解决方案：以矩阵形式布置的两个或更多个像素11在公共节点13上每n个并行连接以形成两个或更多个像素块12.每个像素块12包括n个传送门TG <1> -TG n ，用于打开和关闭连接n个光电转移元件PD 1 -PD n 公共节点13，每个光电转移元件PD＆lt; SB＆gt; -PD＆lt; SB＆gt; n＆gt;和公共节点13.对于每个像素块12，公共复位晶体管Tr 用于复位整个像素11的RST 和用于放大从n个像素11读出的信号的公共放大晶体管Tr AMP 被提供在像素块12的外部。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2004055969A Nonvolatile semiconductor storage element and manufacturing method 有权
公开(公告)号：JP2004055969A
公开(公告)日：2004-02-19
申请号：JP2002213900
申请日：2002-07-23
申请人： Asahi Glass Co Ltd , Mitsumasa Koyanagi , 小柳光正 , 旭硝子株式会社
发明人： KOYANAGI MITSUMASA , TAKADA MASAAKI , KONDO SHINJI
IPC分类号： C23C14/06 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42348 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/7888 , Y10S977/773 , Y10S977/936
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage element capable of decreasing a data write and erasure time, remarkably increasing the number of rewrite times at the same time, and operating at a low power consumption. SOLUTION: In the nonvolatile semiconductor storage element, an electric charge hold layer 3 adjacent to a tunnel insulating film 2 is made of an electric insulating insulation layer 3b. The layer 3 comprises one kind of a single element substance or a compound or more acting like a floating gate whose particle diameter is 5nm or below and independently and dispersingly containing ultra-fine particles 3a, at a surface density of 10 +12 to 10 +14 sets of particles per cm 2 of the electric charge hold layer 3. COPYRIGHT: (C)2004,JPO

7. 发明专利

JP2003076670A Network device, and processing system 审中-公开
标题翻译：网络设备和处理系统
公开(公告)号：JP2003076670A
公开(公告)日：2003-03-14
申请号：JP2002151849
申请日：2002-05-27
申请人： Mitsumasa Koyanagi , Hiroyuki Kurino , Hiroshi Sato , Tohoku Techno Arch Co Ltd , Visual Technology Kk , ビジュアルテクノロジー株式会社 , 浩佐藤 , 光正小柳 , 浩之栗野 , 株式会社東北テクノアーチ
发明人： KOYANAGI MITSUMASA , KURINO HIROYUKI , SATO HIROSHI
IPC分类号： G06F13/14 , G06F12/06 , G06F15/167 , G06F15/173 , H04L12/44
摘要： PROBLEM TO BE SOLVED: To perform the communication between communication nodes at a high speed with a simple configuration. SOLUTION: Processing elements 301-304 are connected to local ports 212215, and an external node is connected to remote ports 216a and 216b. The local ports 212-215 are connected to a cast memory 201 in common, and a message from one communication node is broadcast to other communication nodes. In addition, each local port is connected to pier-to-pier memories 206-211 in a 1:1 manner to exchange the messages to each other. The external node performs writing in memories 202-205 for remote communication via the remote port 216a, performs the communication to a corresponding local port in a 1:1 manner, and also performs the broadcast communication to the local ports 212-215 by using a board-cast memory 201.
摘要翻译：要解决的问题：以简单的配置高速地进行通信节点之间的通信。解决方案：处理元件301-304连接到本地端口212215，并且外部节点连接到远程端口216a和216b。本地端口212-215共同连接到投射存储器201，并且来自一个通信节点的消息被广播到其他通信节点。此外，每个本地端口以1:1的方式连接到码头到码头存储器206-211，以将消息彼此交换。外部节点在存储器202-205中执行用于经由远程端口216a的远程通信的写入，以1:1的方式对相应的本地端口进行通信，并且还通过使用本地端口212-215进行到本地端口212-215的广播通信板式存储器201。

8. 发明专利

JP2003067350A Processing system 审中-公开
标题翻译：加工系统
公开(公告)号：JP2003067350A
公开(公告)日：2003-03-07
申请号：JP2002151848
申请日：2002-05-27
申请人： Mitsumasa Koyanagi , Hiroyuki Kurino , Hiroshi Sato , Tohoku Techno Arch Co Ltd , Visual Technology Kk , ビジュアルテクノロジー株式会社 , 浩佐藤 , 光正小柳 , 浩之栗野 , 株式会社東北テクノアーチ
发明人： KOYANAGI MITSUMASA , KURINO HIROYUKI , SATO HIROSHI
IPC分类号： G06F13/14 , G06F12/06 , G06F15/167 , G06F15/173
摘要： PROBLEM TO BE SOLVED: To perform fast communication among a plurality of processor elements. SOLUTION: An address space of a microprocessor 305 of processing elements 301-304 adopts a memory mapped I/O system and deals with an address space of a main memory and an I/O address space unitiedly. The address space consists of the main memory address space 401 and the I/O address space 402. A broadcast area 403, a first local port area 404, a second local port area 405, a third local port area 406, a fourth local port area 407, a remote port window area 408 and other I/O device area 409 are allocated in the I/O address space 402. The remote port window area 408 receives data from an external system.
摘要翻译：要解决的问题：为了在多个处理器元件之间执行快速通信。解决方案：处理元件301-304的微处理器305的地址空间采用存储器映射I / O系统，并且一起处理主存储器和I / O地址空间的地址空间。地址空间由主存储器地址空间401和I / O地址空间402组成。广播区域403，第一本地端口区域404，第二本地端口区域405，第三本地端口区域406，第四本地端口区域407，远程端口窗口区域408和其他I / O设备区域409被分配在I / O地址空间402中。远程端口窗口区域408从外部系统接收数据。

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