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1. 发明专利

JP5383874B2 Integrated circuit device having a three-dimensional stacked structure 有权
公开(公告)号：JP5383874B2
公开(公告)日：2014-01-08
申请号：JP2012162142
申请日：2012-07-20
申请人：光正小柳
发明人：光正小柳
IPC分类号： H01L25/18 , H01L21/60 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/16 , H01L2924/13091 , H01L2924/00

2. 发明专利

JP4063944B2 Method of manufacturing a three-dimensional semiconductor integrated circuit device 失效
公开(公告)号：JP4063944B2
公开(公告)日：2008-03-19
申请号：JP6347698
申请日：1998-03-13
申请人：光正小柳 , 浩之栗野 , 独立行政法人科学技術振興機構
发明人：光正小柳 , 浩之栗野
IPC分类号： H01L27/00 , H01L27/12 , H01L21/02
CPC分类号： H01L2224/16145

3. 发明专利

JP2005340768A Many-valued non-volatile semiconductor memory element and its manufacturing method 审中-公开
标题翻译：多值非易失性半导体存储元件及其制造方法
公开(公告)号：JP2005340768A
公开(公告)日：2005-12-08
申请号：JP2005030860
申请日：2005-02-07
申请人： Asahi Glass Co Ltd , Mitsumasa Koyanagi , 光正小柳 , 旭硝子株式会社
发明人： TAKADA MASAAKI , KOYANAGI MITSUMASA
IPC分类号： H01L21/316 , H01L21/8247 , H01L27/115 , H01L29/786 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a many-valued non-volatile semiconductor memory element which can perform a stable many-valued memory operation and can keep a sufficient memory window, and to provide its manufacturing method. SOLUTION: The structure is formed on a semiconductor substrate 1 and includes a source area 6, a drain area 7, a tunnel insulating layer 2 formed on a channel forming area, a charge holding layer 3 holding a charge introduced from a channel, an inter-gate insulating layer 4, and a control gate layer 5. The charge holding layer 3 is composed of ultra fine particles(work function is 4.2 eV or less) which are separately dispersed at a density of 10 12 -10 14 /cm 3 and function as a floating gate of a diameter of 5 nm or smaller, and a base insulator(an amorphous substance having an electronic affinity of 1.0 eV or less). COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以执行稳定的多值存储器操作并且可以保持足够的存储器窗口并提供其制造方法的多值非易失性半导体存储器元件。解决方案：结构形成在半导体衬底1上，包括源极区6，漏极区7，形成在沟道形成区上的隧道绝缘层2，电荷保持层3，其保持从沟道引入的电荷，栅极间绝缘层4和控制栅极层5.电荷保持层3由以10 <12>的密度分开分散的超细颗粒（功函数为4.2eV以下） / SP> -10 14 / cm 3 ，并且用作直径为5nm以下的浮栅，以及基极绝缘体（具有电子亲和性的非晶体 1.0eV以下）。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP5007127B2 Manufacturing method and apparatus for an integrated circuit device using a self-organizing function 有权
公开(公告)号：JP5007127B2
公开(公告)日：2012-08-22
申请号：JP2006553851
申请日：2005-12-28
申请人：光正小柳
发明人：光正小柳
IPC分类号： H01L25/04 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/6835 , H01L21/568 , H01L21/6836 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68313 , H01L2221/68327 , H01L2221/68354 , H01L2221/68363 , H01L2224/0401 , H01L2224/13147 , H01L2224/13184 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/16 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/32145 , H01L2224/73104 , H01L2224/73204 , H01L2224/75 , H01L2224/7598 , H01L2224/78743 , H01L2224/81097 , H01L2224/81143 , H01L2224/81193 , H01L2224/81201 , H01L2224/81801 , H01L2224/81907 , H01L2224/83193 , H01L2224/838 , H01L2224/83907 , H01L2224/95145 , H01L2224/95146 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/12043 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/15788 , H01L2224/81 , H01L2224/83 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/01031
摘要： In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor chips 13 are temporarily adhered to corresponding temporary adhesion regions 72a of a carrier substrate 73a by way of sticky material. The carrier substrate 73a is then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portions 12 of the chips 13 on the carrier substrate 73a with corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portions 12 to the predetermined positions, the chips 13 are attached to the support substrate or the circuit layer with a desired layout.

5. 发明专利

JP2007073775A Method for manufacturing integrated circuit device having three-dimensional laminated structure 有权
标题翻译：制造具有三维层叠结构的集成电路装置的方法
公开(公告)号：JP2007073775A
公开(公告)日：2007-03-22
申请号：JP2005259824
申请日：2005-09-07
申请人： Mitsumasa Koyanagi , 光正小柳
发明人： KOYANAGI MITSUMASA
IPC分类号： H01L21/60 , H01L21/3205 , H01L23/52
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L24/10 , H01L24/13 , H01L24/90 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13 , H01L2224/13147 , H01L2224/83192 , H01L2224/83194 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/18301 , H01L2924/19043 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit device having a three-dimensional laminated structure by which electrically insulating adhesive can be reliably arranged in gaps between semiconductor circuit layers and the necessity for removing excessive adhesive protruding from the gaps can be avoided. SOLUTION: Several buried interconnections (conductive plugs) 15 are formed in a first semiconductor circuit layer 1a, and their ends are exposed from the reverse side of the first semiconductor circuit layer 1a. Several bump electrodes 43a corresponding to the plugs 15 are formed on the surface of a second semiconductor circuit layer 2. An electrically insulating adhesive film 44a which is patterned in such a way that it does not overlap the bump electrodes 43a is formed on the surface of the second semiconductor circuit layer 2. After that, the buried interconnections 15 and the bump electrodes 43a are mechanically connected with one another by opposing the reverse side of the first semiconductor circuit layer 1a to the front surface of the second semiconductor circuit layer 2, bringing them closer to each other, and crushing at least a part of the bump electrodes 43a while the adhesive film 44a is deformed between the layers 1a and 2. At the same time, the circuit layers 1a and 2 are bonded by the adhesive film 44a. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种具有三维叠层结构的集成电路器件的制造方法，通过该方法可以将电绝缘性粘合剂可靠地布置在半导体电路层之间的间隙中，并且必须除去从可以避免间隙。解决方案：在第一半导体电路层1a中形成多个埋入互连（导电插塞）15，并且它们的端部从第一半导体电路层1a的背面露出。在第二半导体电路层2的表面上形成有与插头15相对应的多个凸起电极43a。以与突起电极43a不重叠的方式构图的电绝缘粘合膜44a形成在第二半导体电路层2.之后，通过将第一半导体电路层1a的反面与第二半导体电路层2的正面相对，将掩埋布线15和突起电极43a相互机械连接，使它们彼此更靠近，并且在粘合剂膜44a在层1a和2之间变形的同时破碎凸起电极43a的至少一部分。同时，电路层1a和2通过粘合膜44a粘合。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2005328029A Nonvolatile semiconductor storage element and method for manufacturing the same 审中-公开
标题翻译：非挥发性半导体存储元件及其制造方法
公开(公告)号：JP2005328029A
公开(公告)日：2005-11-24
申请号：JP2005030859
申请日：2005-02-07
申请人： Asahi Glass Co Ltd , Mitsumasa Koyanagi , 光正小柳 , 旭硝子株式会社
发明人： TAKADA MASAAKI , KOYANAGI MITSUMASA
IPC分类号： B82B1/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage element contributing to improvement in the speed of data rewriting operation and the miniaturization and high density of the element, and to provide a method for manufacturing the nonvolatile semiconductor storage element. SOLUTION: The nonvolatile semiconductor storage element is provided with a source area 6 and a drain area 7 which are formed on a semiconductor substrate 1, a tunnel insulating layer 2 formed on a channel formation area, a charge holding layer 3 for holding charge injected from the channel, an inter-gate insulating layer 4, and a control gate 5. The charge holding layer 3 is constituted of ultrafine particulates (a work function is ≥4.2 eV) which are independently dispersed at the density of 10 12 to 10 14 particulates/cm 3 serving as floating gates having grain size of ≤5 nm, and a mother phase insulator (amorphous substance of which electron affinity is ≤1.0 eV). COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种有助于提高数据重写操作的速度和元件的小型化和高密度的非易失性半导体存储元件，并且提供一种用于制造非易失性半导体存储元件的方法。解决方案：非易失性半导体存储元件设置有形成在半导体基板1上的源极区域6和漏极区域7，形成在沟道形成区域上的隧道绝缘层2，用于保持的电荷保持层3 从沟道注入的电荷，栅极间绝缘层4和控制栅极5.电荷保持层3由以10 12 至10 14 颗粒/ cm 3 / SP>作为具有≤5nm的晶粒尺寸的浮动栅极，以及母相绝缘体（其中电子亲和力≤1.0eV）。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP4137328B2 Method of manufacturing a three-dimensional semiconductor integrated circuit device 有权
公开(公告)号：JP4137328B2
公开(公告)日：2008-08-20
申请号：JP37561999
申请日：1999-12-28
申请人：富士ゼロックス株式会社 , 光正小柳
发明人：宣明宮川 , 光正小柳 , 泰典岡野
IPC分类号： H01L27/00

8. 发明专利

JP3920249B2 Optical waveguide 有权
公开(公告)号：JP3920249B2
公开(公告)日：2007-05-30
申请号：JP2003196759
申请日：2003-07-14
申请人：光正小柳 , 日立化成工業株式会社
发明人：信生宮寺 , 光正小柳 , 裕本田 , 保宏桑名
IPC分类号： G02B6/13 , G02B6/122

9. 发明专利

JPWO2003041167A1 低誘電率材料膜を用いた半導体装置およびその製造方法有权
公开(公告)号：JPWO2003041167A1
公开(公告)日：2005-03-03
申请号：JP2003543101
申请日：2002-11-05
申请人：小柳光正 , 光正小柳
发明人：小柳　光正 , 光正小柳
IPC分类号： H01L27/00 , H01L21/02 , H01L21/336 , H01L21/768 , H01L21/822 , H01L21/8234 , H01L21/84 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/786
CPC分类号： H01L21/84 , H01L21/76898 , H01L21/8221 , H01L27/0688 , H01L27/12 , H01L29/42384 , H01L29/66772 , H01L29/78603 , H01L29/78648 , H01L2224/2919 , H01L2224/32145 , H01L2924/00014
摘要：シリコン以外の低誘電率基板を用いて動作速度の高速化に対応できる半導体装置である。基板(11)と、比誘電率がシリコンより低い低誘電率材料膜(12)とからなる基体(10)を設ける。基体(10)の表面に、MOSトランジスタ(30)を含む半導体素子層を接着して積層する。MOSトランジスタ(30)は、島状の単結晶Si膜(31)を用いて形成し、絶縁膜(15)、(16)、(17)の内部に埋設させる。半導体素子層の上に多層配線構造(18)を形成し、MOSトランジスタ(30)に電気的接続する。基体(10)の裏面に、信号のリターンパスとして機能する電極(20)を形成する。基体(10)に電極(20)を形成するのに代えて、基体(10A)の裏面に複数の電極(20A)を配置して基体(10A)をインターポーザとして構成することもできる。

10. 发明专利

JP2012209596A Method of manufacturing integrated circuit device having three-dimensional lamination structure 有权
标题翻译：制造具有三维层叠结构的集成电路装置的方法
公开(公告)号：JP2012209596A
公开(公告)日：2012-10-25
申请号：JP2012162142
申请日：2012-07-20
申请人： Mitsumasa Koyanagi , 光正小柳
发明人： KOYANAGI MITSUMASA
IPC分类号： H01L25/065 , H01L21/60 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an integrated circuit device with a three-dimensional lamination structure capable of arranging an electrical insulating adhesive agent in a clearance between semiconductor circuit layers with certainty, and of eliminating a need for removing a surplus adhesive agent overflowed from the clearance.SOLUTION: A plurality of embedded wires (conductive plugs) 15 are formed inside a first semiconductor circuit layer 1a, and their ends are exposed to a rear face of the first semiconductor circuit layer 1a. A plurality of bump electrodes 43a are formed on a surface of a second semiconductor circuit layer 2 so as to correspond to the respective plugs 15. An electrical insulating adhesive agent film 44a patterned in a shape not overlapped with the bump electrodes 43a is formed on the surface of the second semiconductor circuit layer 2. Thereafter, the rear face of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2 are opposed and approached to each other, and therebetween, at least a part of the respective bump electrodes 43a are compressed while deforming the adhesive agent film 44a to mechanically connect the embedded wires 15 and the bump electrodes 43a mutually and adhere both circuit layers 1a and 2 by the adhesive agent film 44a.
摘要翻译：要解决的问题：提供一种制造集成电路器件的方法，该集成电路器件具有能够确定地在半导体电路层之间的间隙中布置电绝缘粘合剂的三维层压结构，并且不需要去除剩余的粘合剂从间隙溢出。解决方案：在第一半导体电路层1a内部形成有多个嵌入导线（导电插塞）15，并且它们的端部暴露于第一半导体电路层1a的背面。在第二半导体电路层2的表面上形成多个凸起电极43a，以便与各个插塞15相对应。形成与凸起电极43a不重叠的形状的电绝缘粘合剂膜44a形成在此后，第一半导体电路层1a的背面和第二半导体电路层2的表面彼此相对并接近，并且在它们之间，至少部分各个凸起电极43a在粘合剂膜44a变形的同时被压缩，以相互间接地连接嵌入线15和凸起电极43a，并且通过粘合剂膜44a粘附两个电路层1a和2。版权所有（C）2013，JPO＆INPIT

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