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1. 发明专利

JPH04360414A PRIORITY CIRCUIT 失效
公开(公告)号：JPH04360414A
公开(公告)日：1992-12-14
申请号：JP16240391
申请日：1991-06-07
申请人： MARUOKA TAKAYA
发明人： MARUOKA TAKAYA
IPC分类号： G06F13/00 , H03K17/00
摘要： PURPOSE:To surely take priority even with a minute time difference by deciding the priority without using a CLOCK signal so as to extreamly simplify the circuit constitution. CONSTITUTION:An input signal A is inputted to one input terminal S1 of a 1st stage RS-FF 35a via an inverter 37a and an input signal B is inputted to the other input terminal S2 of a via an inverter 37b. The input signal A is inputted to a 1st AND circuit 39a and the inverse of Q2 output is inputted to a 2nd stage RS-FF 35b and the input signal B and the Q2 output of the 2nd-stage RS-FF 35b are inputted to a 2nd AND circuit. PA, PB are used for decision outputs.

2. 发明专利

JPS59228418A ENCODING DEVICE 失效
公开(公告)号：JPS59228418A
公开(公告)日：1984-12-21
申请号：JP10292083
申请日：1983-06-10
申请人： INT SYSTEM IND , MARUOKA TAKAYA
发明人： MARUOKA TAKAYA
IPC分类号： H03M1/54 , H03K13/20
摘要： PURPOSE:To reduce the A/D converting time by providing a count means conducting up-count until an output of a voltage state discriminating means is inverted after discharge and a count means conducting down-count until the output is inverted again after the former inversion. CONSTITUTION:When the charging of a capacitor C is finished, an analog switch S2 is opened and an analog switch S1 is switched into closing and the capacitor C is discharged. A clock pulse is inputted to an up-down counter 6 in this case. When the terminal voltage of the capacitor C rises and an output of the comparator 4 is inverted, the analog switch S1 is switched into opening and an analog switch S3 is switched into closing. Then the capacitor C is dischargd and the clock pulse is inputted to a down counter 7 until the output of the comparator 4 is inverted.

3. 发明专利

JPS59225446A READ ONLY FIXED STORAGE DEVICE AND DIVIDER USING THIS STRAGE DEVICE 失效
公开(公告)号：JPS59225446A
公开(公告)日：1984-12-18
申请号：JP9946383
申请日：1983-06-06
申请人： INT SYSTEM IND , MARUOKA TAKAYA
发明人： MARUOKA TAKAYA
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535 , G11C17/00
摘要： PURPOSE:To reduce the division arithmetic time by executing sequentially addition for the number of difference in digit between a dividend and a divisor at all times, subtraction once, and memory access of an abridged quotient ROM and an abridged remainder ROM. CONSTITUTION:In setting a dividend and a divisor respecively to a dividend register 1 and a divisor register 2, a quotient data and a remainder data are outputted respectively from the abridged quotient ROM3 and the abridged remainder ROM4. Then the added value of low-order three bits of the remainder data and the divided is outputted from an adder 5. The divisor is subtracted from this sum by a subtractor 6 and a sign is discriminated by a sign discriminating circuir 7. A quotient switching section changes over signals based on a detection signal from an all zero detecting circuit 14 and a remainder switching section 13 executes the changeover based on a detecting signal from the all zero detecting circuit 14 and the output signal from the sign discrimination circuit 7. Thus, the quotient and remainder are outputted based on the output of the ROMs 3, 4, 9 and 10.

4. 发明专利

JPH0472817A DIGITAL PLL CIRCUIT 失效
公开(公告)号：JPH0472817A
公开(公告)日：1992-03-06
申请号：JP18268590
申请日：1990-07-12
申请人： MARUOKA TAKAYA
发明人： MARUOKA TAKAYA
IPC分类号： H03L7/06
摘要： PURPOSE:To attain all signal processing with a digital circuit and to vary the frequency of an output signal smoothly over a wide range by obtaining the output signal from a carry output or a borrow output of a variable notation counter. CONSTITUTION:The circuit is provided with a variable notation counter 24 whose initial value or final value is set by a count of an up-down counter 23 and with a circuit 25 generating a feedback signal from a carry output (in the case of an up-counter) or a borrow output (in the case of a down-counter) of the variable notation counter 24. Then the carry output or the borrow output of the variable notation counter 24 is fed to an optional frequency division ratio frequency divider circuit 26 as required, from which an output signal fOU is obtained. Thus, all signal processing is implemented by a digital circuit, circuit integration of the PLL circuit is attained, the reliability is improved and the cost is reduced and the frequency of the output signal is varied smoothly over a wide range regardless of the digital PLL circuit.

5. 发明专利

JPS6030176A VARIABLE CURRENT TYPE NEGATIVE RESISTANCE CIRCUIT 失效
公开(公告)号：JPS6030176A
公开(公告)日：1985-02-15
申请号：JP13749583
申请日：1983-07-29
申请人： INT SYSTEM IND , MARUOKA TAKAYA
发明人： MARUOKA TAKAYA
IPC分类号： H01L29/70 , H01L21/33 , H01L21/331 , H01L29/73 , H01L29/74
摘要： PURPOSE:To enable to change arbitrarily the voltage-ampere negative resistance characteristic of a negative resistance circuit, and to obtain the circuit having wide general-purpose properties by a method wherein the circuit is constructed of a P-N-P transistor, an N-P-N transistor and variable resistors. CONSTITUTION:A part of the collector current of a P-N-P transistor Tr1 acts as the base current of an N-P-N transistor Tr2, and a part of the collector current of the transistor Tr2 acts as the base current of the transistor Tr1 to construct a positive feedback circuit. Accordingly, relation between a current (i) to flow in a current inflow terminal (a) and an interterminal voltage V between the terminal (a) and a current outflow terminal (b) is changed according to the values of variable resistors VR1, VR2, and when the circuit is made to have the characteristic P1, the circuit displays a negative resistance characteristic at a current region Ai, and the circuit becomes unstably.

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