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2. 发明专利

JPS59228417A ANALOG-DIGITAL CONVERTER 失效
公开(公告)号：JPS59228417A
公开(公告)日：1984-12-21
申请号：JP10264583
申请日：1983-06-10
申请人： HITACHI LTD
发明人： UENO MASAHIRO , SASE TAKASHI , KURITA KOUZABUROU
IPC分类号： H03M1/50 , H03M1/06 , H03K13/20
摘要： PURPOSE:To eliminate the effect of leakage current on an AD converting gain by driving a switch connected to an integration circuit among switches being components of a switched capacitor circuit in an identical prescribed period. CONSTITUTION:A switch Sr2 of a reference charge injection circuit 12 repeats turning on/off at all times in synchronizing with the operation of a switch Si2 and only a switch Sr1 is turned in synchronizing with an output of a comparator circuit 14. Thus, since the leakage current does not give any effect on the gain, the gain is not largely susceptible to the effect of conditions such as ambient temperature and manufacture process.

6. 发明专利

JPS5830226A DIGITAL/ANALOG CONVERTING CIRCUIT 失效
公开(公告)号：JPS5830226A
公开(公告)日：1983-02-22
申请号：JP12833981
申请日：1981-08-17
申请人： NAKAMICHI CORP
发明人： UCHIKOSHI KOUJI
IPC分类号： H03M1/82 , H03K13/20
摘要： PURPOSE:To elevate accuracy of conversion and its speed, by setting the second constant-current value generated in the period for responding to pulse width, to the first constant-current value, in accordance with weight of a lower bit against an upper bit. CONSTITUTION:A digital signal which has set that which has quantized an analog signal by (n) bits, to an upper bit, and has set that which has further quantized an error portion due to quantization, to a lower bit is divided into the upper bit and the lower bit, which are set to pulse width signals P1, P2, respectively. Subsequently, the pulse width signals P1, P2 and its inverted signals -P1, -P2 are inputted to an analog voltage forming circuit 7, drive differential amplifiers 8, 9, and control currents I1, I2 of constant-current circuits 10, 11. In this case, the constant-currents I1, I2 set the current I2 to the current I1 in accordance with a difference of weights of the upper bit and the lower bit.

7. 发明专利

JPS5827430A DIGITAL-TO-ANALOG CONVERTING METHOD 失效
公开(公告)号：JPS5827430A
公开(公告)日：1983-02-18
申请号：JP12548681
申请日：1981-08-11
申请人： NAKAMICHI CORP
发明人： UCHIKOSHI KOUJI
IPC分类号： H03K9/08 , H03M1/82 , H03K13/20
摘要： PURPOSE:To prevent the generation of sencondary distortion, by performing the conversion to a pulse width signal based on the sampled digital signals and the complement of the said digital signals, and performing analog conversion through a filter. CONSTITUTION:A pulse width signal forming circuit 1 generates a pulse width signal in which a digiral signal of required bits is taken as the center of pulse width for a prescribed time of the sampling period and the value is changed depending on each data. A pulse width signal forming circuit 2 converts a complemented digital signal into the pulse width signal. A mixer circuit 4 inverts one of two pulse width signals and adds it to the other. As a result, the obtained pulse width signal is converted into an analog signal through a smoothing filter 5. Thus, the secondary harmonics are cancelled and the generation of distortion can be generated.

9. 发明专利

JPS57194626A DA CONVERTER 失效
公开(公告)号：JPS57194626A
公开(公告)日：1982-11-30
申请号：JP8056681
申请日：1981-05-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： TAKEBE HIDEJI , KOBAYASHI HIROSHI
IPC分类号： H03M1/82 , H03M1/00 , H03K13/20
摘要： PURPOSE:To decrease the time constant of an integrating circuit and to increase the operation speed by preventing a H-level period of output pulses from being crowded at some position. CONSTITUTION:When five-bit digital data D1-D5 are inputted, the value which corresponds to the high-order two-bit data D4 and D5 is preset in a two-bit programmable counter 2 through a presetting circuit 3 by a presetting signal QL. The programmable counter 2 starts counting a clock Q0 at the rising point of the QL and when its contents reach the prescribed preset value, it outputs a signal 42 to a gate circuit 15. Further, a reference clock Q0 is applied to a frequency dividing circuit 1 to obtain outputs Q3-Q5 of frequency dividers as the 3rd, 4th and 5th stages, and those outputs Q3-Q5 and QL are supplied to a decoding circuit 16 to obtain outputs Q3*-Q5*. Those outputs are controlled by AND circuits 31-33 by using the data D1-D3, and a pulse output 41 is obtained from an OR circuit 34. Pulse outputs 41 and 43 are led out through an OR circuit 35 and an integrating circuit 4 to obtain the analog output which corresponds to the digital data D1-D5.

10. 发明专利

JPS57188131A PULSE WIDTH MODULATION CIRCUIT 失效
公开(公告)号：JPS57188131A
公开(公告)日：1982-11-19
申请号：JP7371581
申请日：1981-05-15
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMAGUCHI SEIJI , CHIYUUNO MASARU , YABU TOSHIOMI , OOTA YUTAKA
IPC分类号： H03M1/82 , H03K13/20
摘要： PURPOSE:To obtain a pulse width modulation circuit without malfunction, by outputting an output pulse until a counter is again preset, through the counting of a counter is stopped, when the counter preset with a digital value counts a maximum counting value. CONSTITUTION:After digital modulation signals d1-dn are stored in a preset circuit 4, they are preset in a binary counter 1. A clock (a) is applied to the counter 1 via a gate 5 and the counter 1 counts this clock (a). When the content of the binary counter 1 reaches a maximum count value, a detector 6 detects it, a detected output is applied to an output generator 7 and a gate 5 to close the gate 5. At every period corresponding to a period when the counter 1 reaches the maximum value from zero, the counter 1 is preset from the preset circuit 4. An output pulse width corresponding to the digital modulation signals d1-dn can be obtained from the output circuit 7.

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