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81. 发明专利

JP2012253584A Cdr circuit, receiver, and transmission and reception system 审中-公开
标题翻译： CDR电路，接收器，传输和接收系统
公开(公告)号：JP2012253584A
公开(公告)日：2012-12-20
申请号：JP2011124790
申请日：2011-06-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HAMANO DAISUKE , USUKINU TATSUNORI
IPC分类号： H04L7/02 , H03L7/08 , H03L7/085
CPC分类号： H04L7/0332 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/089 , H03L7/091
摘要： PROBLEM TO BE SOLVED: To improve phase follow-up accuracy of a CDR circuit using nonlinear phase comparator, receiver, and a reproduction clock of a transmission and reception system.SOLUTION: The CDR circuit 106, receiver 101, and transmission and reception system 100 applies weighting to an output of a nonlinear phase comparator into which reception data 105 and a reproduction clock 119 are input according to a delay or an advance of a clock with a phase difference of the reception data to the reproduction clock, and the phase of the reproduction clock is adjusted based on the weighted output.
摘要翻译：要解决的问题：使用非线性相位比较器，接收机和发送和接收系统的再现时钟来提高CDR电路的相位跟踪精度。解决方案：CDR电路106，接收机101和发送和接收系统100对非线性相位比较器的输出应用加权，根据延迟或前进，输入接收数据105和再现时钟119 具有接收数据与再现时钟的相位差的时钟，并且基于加权输出来调整再现时钟的相位。版权所有（C）2013，JPO＆INPIT

82. 发明专利

JP5023605B2 Delay adjustment circuit and a method of controlling the same 有权
公开(公告)号：JP5023605B2
公开(公告)日：2012-09-12
申请号：JP2006216587
申请日：2006-08-09
申请人：富士通セミコンダクター株式会社
发明人：茂高朝野
IPC分类号： H03K5/13 , H03L7/081
CPC分类号： H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0891

83. 发明专利

JP4992020B2 Delay lock loop and a method for clock generation 有权
公开(公告)号：JP4992020B2
公开(公告)日：2012-08-08
申请号：JP2004192845
申请日：2004-06-30
申请人：エスケーハイニックス株式会社SK hynix Inc.
发明人：鍾太郭
IPC分类号： G06F1/06 , G11C11/4076 , G11C11/407 , H03K5/135 , H03K5/26 , H03L7/07 , H03L7/081 , H03L7/087
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/087

84. 发明专利

JP2012039357A Cdr circuit, receiving apparatus and communication system 有权
标题翻译： CDR电路，接收装置和通信系统
公开(公告)号：JP2012039357A
公开(公告)日：2012-02-23
申请号：JP2010177337
申请日：2010-08-06
申请人： Sony Corp , ソニー株式会社
发明人： TANAKA TOMOKAZU , KIKUCHI HIDEKAZU
IPC分类号： H04L7/02 , H03K5/15 , H03L7/08 , H03L7/081
CPC分类号： H04L7/033 , H03L7/07 , H03L7/0807 , H03L7/0816 , H04L7/0037 , H04L7/044
摘要： PROBLEM TO BE SOLVED: To provide a CDR circuit, a receiving apparatus and a communication system that can implement high speed and resistance to jitter input and suppress the occurrence of signal errors by a simple circuit configuration.SOLUTION: A CDR circuit 310 includes: a frequency divider 320 that includes delay elements 312-1 to 312-4 and extracts a clock when triggered by a data input with periodic signal transitions inserted; and latches 315-1 to 315-8 that latches the input data signal in synchronism with the clock extracted by the frequency divider.
摘要翻译：要解决的问题：提供一种能够实现高速度和抗抖动输入的CDR电路，接收装置和通信系统，并且通过简单的电路配置来抑制信号错误的发生。解决方案：CDR电路310包括：分频器320，其包括延迟元件312-1至312-4，并且在由周期性信号转换插入的数据输入触发时提取时钟; 以及锁存器315-1至315-8，其与由分频器提取的时钟同步地锁存输入数据信号。版权所有（C）2012，JPO＆INPIT

85. 发明专利

JP2011527073A Delay compensation method and system for global pll based timing recovery loop 有权
公开(公告)号：JP2011527073A
公开(公告)日：2011-10-20
申请号：JP2011517088
申请日：2009-06-30
申请人：インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人：エレフテリオウ、エヴァンジェロス , オエルサー、セダ , ハッチンス、ロバート
IPC分类号： G11B20/14 , H03L7/06
CPC分类号： H03L7/07 , G11B20/10009 , G11B20/10222 , G11B20/10425 , G11B20/1403 , G11B2220/90 , H03L7/085 , H03L7/22
摘要：【課題】グローバルＰＬＬベース・タイミング・リカバリ・ループの遅延補償方法及びシステムを提供する。
【解決手段】一実施形態のシステムは、個々のチャネルに関連する誤差信号をそれぞれ受け取る複数の入力を備えたグローバルＰＬＬ回路と、前記グローバルＰＬＬ回路と結合された遅延補償回路と、を含む。一実施形態の方法は、個々のチャネルにそれぞれ関連する複数の誤差信号を受け取るステップと、前記誤差信号に１つ又は複数の遅延補償信号を適用するステップと、前記チャネルのそれぞれに関する位相誤差出力信号を出力するステップと、を含む。
【選択図】図５

86. 发明专利

JP4787395B2 Display device 有权
公开(公告)号：JP4787395B2
公开(公告)日：2011-10-05
申请号：JP2000056715
申请日：2000-03-02
申请人： Necディスプレイソリューションズ株式会社
发明人：幸一郎原 , 泰夫村上
IPC分类号： G09G3/20 , G09G3/36 , H03L7/07 , H03L7/081 , H03L7/091 , H04N5/06 , H04N5/12 , H04N5/66
CPC分类号： H03L7/091 , G09G5/008 , H03L7/07 , H03L7/0812 , H04N5/126
摘要： An object is to eliminate the effect of jitter in a sampling clock to realize proper sampling of a video signal. An A/D converter (1) samples a video signal in synchronization with a sampling clock (VCLK) at a rate of a period which is ½ times the video period. The phase of the sampling clock (VCLK) is corrected in a phase correcting circuit (9). The sampled signals are held alternately as data (DL) and (DR) in two latches (14) (15). A data switching portion (16) selects output signals from one of the two latches (14) and (15). A calculating portion (21) calculates an absolute difference value (DeltaD) between the data (DL) and (DR) in each video period. A calculating portion (22) calculates a maximum value (Dmax) among the absolute difference values (DeltaD) in one frame. A phrase control portion (19) controls the phase correcting circuit (9) and the data switching portion (16) so that a video signal processing circuit (2) can receive sampled signals which are sampled signals which are sampled at a phase corresponding to the center of a rising transition which the maximum value (Dmax) makes as the phase varies.

87. 发明专利

JP2011061729A Clock recovery circuit and data reproduction circuit 有权
标题翻译：时钟恢复电路和数据复制电路
公开(公告)号：JP2011061729A
公开(公告)日：2011-03-24
申请号：JP2009212290
申请日：2009-09-14
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKADA SHUICHI
IPC分类号： H04L7/02 , H03L7/06 , H03L7/08
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091
摘要： PROBLEM TO BE SOLVED: To provide a clock recovery circuit capable of reducing clock jitter and data reproduction circuit. SOLUTION: A clock recovery circuit comprises: a sampler 13 for outputting sampling data obtained by sampling a serial input signal synchronously to a first clock signal; a phase comparator circuit 14 for outputting a serial phase information signal representing a phase relationship between the first clock signal and a clock of the serial input signal based on the sampling data; a serial/parallel converter circuit 17 for outputting a parallel phase information signal obtained by performing serial/parallel conversion on the serial phase information signal synchronously to a second clock signal; a digital filter circuit 16 for arithmetically operating a phase deviation signal and a phase delay/advance signal based on the parallel phase information signal; a phase control amount processing circuit 20 for outputting a phase control signal generated based on the phase deviation signal and the phase delay/advance signal synchronously to a third clock signal faster than the second clock signal; and a phase interpolation circuit 12 for outputting the first clock signal obtained by adjusting a phase of a reference clock signal inputted from the outside based on the phase control signal. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供能够减少时钟抖动和数据再现电路的时钟恢复电路。解决方案：时钟恢复电路包括：采样器13，用于输出通过与第一时钟信号同步地对串行输入信号进行采样而获得的采样数据; 相位比较器电路14，用于基于采样数据输出表示第一时钟信号和串行输入信号的时钟之间的相位关系的串行相位信息信号; 串行/并行转换器电路17，用于输出通过与第二时钟信号同步地对串行相位信息信号执行串行/并行转换而获得的并行相位信息信号; 数字滤波电路16，用于基于并行相位信息信号运算相位偏差信号和相位延迟/提前信号; 相位控制量处理电路20，用于基于相位偏差信号产生的相位控制信号和相位延迟/提前信号与第二时钟信号比第三时钟信号同步; 以及相位插值电路12，用于输出通过基于相位控制信号调整从外部输入的参考时钟信号的相位而获得的第一时钟信号。版权所有（C）2011，JPO＆INPIT

88. 发明专利

JP2011019281A Frequency-multiplying delay locked loop 有权
标题翻译：频率延迟延迟锁定环
公开(公告)号：JP2011019281A
公开(公告)日：2011-01-27
申请号：JP2010210865
申请日：2010-09-21
申请人： Mosaid Technol Inc , モーセッド・テクノロジーズ・インコーポレイテッドMosaid Technologies 1ncorporated
发明人： DEMONE PAUL W
IPC分类号： G11C11/407 , H03K5/00 , G06F1/08 , H03K5/133 , H03K5/135 , H03K5/15 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/16
CPC分类号： H03L7/06 , H03K5/00006 , H03K5/15046 , H03L7/07 , H03L7/0812 , H03L7/0814 , H03L7/089 , H03L7/16
摘要： PROBLEM TO BE SOLVED: To provide a frequency multiplier circuit which can generate an interface clock or an internal clock serving as a multiple of an external clock.SOLUTION: The frequency multiplier circuit (100) includes a delay line and a clock combining circuit (TOG). The delay line receives at one end thereof a reference clock (102) and generates clock tap outputs from a plurality of period matched delay elements (101). The clock combining circuit (TOG) is responsive to pairs of tap outputs and generates a rising and falling edge of an output clock pulse from the respective tap outputs. An output clock period is shorter than an input clock period. The delay line may be included in a delay-locked loop so as to match the period of the delay elements (101). Further, a plurality of combining circuit cells (TOG) are provided, each having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs and providing complementary outputs. A selector (106) selects an output from one of a pair of complementary outputs of one of the combining cells in response to a selection control signal from a phase detector (112).
摘要翻译：要解决的问题：提供一种可产生接口时钟或内部时钟作为外部时钟的倍数的倍频电路。解码器：倍频电路（100）包括延迟线和时钟组合电路（TOG ）。延迟线在其一端接收参考时钟（102），并从多个周期匹配延迟元件（101）产生时钟抽头输出。时钟组合电路（TOG）响应于抽头输出对，并从各个抽头输出产生输出时钟脉冲的上升沿和下降沿。输出时钟周期短于输入时钟周期。延迟线可以包括在延迟锁定环路中，以便与延迟元件（101）的周期相匹配。此外，提供了多个组合电路单元（TOG），每个组合电路单元具有分别耦合到预定数量的延迟级抽头输出中的一些并提供互补输出的输入。响应于来自相位检测器（112）的选择控制信号，选择器（106）从组合单元之一的一对互补输出中的一个选择输出。

89. 发明专利

JP4549958B2 Delay locked loop circuit 有权
公开(公告)号：JP4549958B2
公开(公告)日：2010-09-22
申请号：JP2005264131
申请日：2005-09-12
申请人：パナソニック株式会社
发明人：英喜吉井 , 康之土居 , 徹岩田 , 史朗崎山 , 貴士平田 , 祐介徳永 , 慎服部 , 志郎道正
IPC分类号： H03L7/081 , H03L7/093
CPC分类号： H03L7/0812 , H03L7/07 , H03L7/0891 , H03L7/0895

90. 发明专利

JP4526194B2 Oversampling clock recovery method and circuit 有权
公开(公告)号：JP4526194B2
公开(公告)日：2010-08-18
申请号：JP2001003667
申请日：2001-01-11
申请人：ルネサスエレクトロニクス株式会社
发明人：中村　　聡
IPC分类号： H03K5/15 , H04L7/033 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/091 , H03L7/099
CPC分类号： H03L7/091 , H03L7/07 , H03L7/0814 , H03L7/087 , H03L7/0995 , H04L7/0337

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