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81. 发明专利

JP2010103541A Direct die bonding using heated bond head 有权
标题翻译：直接连接使用加热的绑定头
公开(公告)号：JP2010103541A
公开(公告)日：2010-05-06
申请号：JP2009245825
申请日：2009-10-26
申请人： Asm Assembly Automation Ltd , エーエスエム・アセンブリー・オートメーション・リミテッドASM Assembly Automation Ltd.
发明人： LI MING , DING YING , TU PING LIANG , LO KING MING , CHUNG KWOK KEE
IPC分类号： H01L21/52 , H01L33/62
CPC分类号： H01L24/83 , H01L24/29 , H01L24/75 , H01L2224/29101 , H01L2224/29111 , H01L2224/29144 , H01L2224/2919 , H01L2224/32506 , H01L2224/83191 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/12041 , H01L2924/157 , H01L2924/15787 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a direct die bonding method for die bonding, which prevents a deficiency of a die bonding method of a conventional technology at least to some extent. SOLUTION: A method is provided for bonding a die comprising a solder layer of a melting point Tm. A bond head is heated to a bond head setting temperature T1, which is higher than Tm, and a substrate is heated to a substrate setting temperature T2, which is lower than Tm. Thereafter, the die is lifted by the bond head, and the die is heated towards temperature T1 to melt the solder layer. The solder layer of the die is pressed onto the substrate to bond the die to the substrate, and thereafter the die is separated from the bond head so that the solder layer is cooled towards T2 and solidifies. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种芯片接合的直接芯片接合方法，其至少在一定程度上防止了传统技术的芯片接合方法的缺陷。解决方案：提供一种用于接合包含熔点Tm的焊料层的管芯的方法。将接合头加热到高于Tm的接合头设定温度T1，将衬底加热到低于Tm的衬底设定温度T2。此后，通过接合头抬起模具，并将模具加热到温度T1以熔化焊料层。将模具的焊料层压在基板上以将模具结合到基板上，然后将模具从结合头分离，使得焊料层朝T2冷却并固化。版权所有（C）2010，JPO＆INPIT

82. 发明专利

JP2009110983A Silicon interposer and semiconductor device package, and semiconductor device incorporating the same 有权
标题翻译：硅插件和半导体器件封装，以及与之相同的半导体器件
公开(公告)号：JP2009110983A
公开(公告)日：2009-05-21
申请号：JP2007278440
申请日：2007-10-26
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： HARUHARA MASAHIRO
IPC分类号： H01L23/32 , H01L23/12 , H01L23/14
CPC分类号： H01L23/49827 , H01L23/49816 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a silicon interposer which will not cause cracks between through-hole electrodes and an insulating film that makes contact with the through-hole electrodes, even if a thermal load is acts repeatedly on the silicon interposer, and to provide a semiconductor device package and a semiconductor device, each incorporating the interposer.
SOLUTION: In the silicon interposer 30 which is held in between a wiring board 40 and a semiconductor element 60 for electrically connecting the wiring board 40 to the semiconductor element 60, the through-hole electrodes 17, for electrically connecting the wiring board 40 to the semiconductor elements 60, are each formed of a base section and a buffer section; the buffer section is formed of a conductive material whose elastic coefficient is lower than that of the conductive material of the base section. The semiconductor device package 50 and the semiconductor device 70, each incorporating the silicon interposer 30, are also provided.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决问题：为了提供一种不会在通孔电极与与通孔电极接触的绝缘膜之间产生裂纹的硅插入件，即使热负荷在硅插入件上反复作用，并提供半导体器件封装和半导体器件，每个都包含插入器。解决方案：在保持在布线板40和用于将布线板40电连接到半导体元件60的半导体元件60之间的硅插入件30中，用于电连接布线板的通孔电极17 40与半导体元件60分别由基部和缓冲部构成，缓冲部由弹性系数低于基部的导电性材料的导电性材料构成。还提供了半导体器件封装50和包括硅插入件30的半导体器件70。版权所有（C）2009，JPO＆INPIT

83. 发明专利

JP2008252087A Structure of semiconductor device package and method of the same 审中-公开
标题翻译：半导体器件封装的结构及其方法
公开(公告)号：JP2008252087A
公开(公告)日：2008-10-16
申请号：JP2008058397
申请日：2008-03-07
申请人： Advanced Chip Engineering Technology Inc , アドバンスドチップエンジニアリングテクノロジーインコーポレイティッドAdvanced Chip Engineering Technology Inc.
发明人： YANG WEN-KUN , CHII-MIN CHEN , HSU HSIEN-WEN
IPC分类号： H01L25/065 , H01L23/12 , H01L25/07 , H01L25/18
CPC分类号： H01L25/50 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/12105 , H01L2224/24137 , H01L2224/24227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2225/06524 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01068 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2224/05099
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device package with good CTE performance and a contraction size providing board-level reliability having satisfactory temperature cycle. SOLUTION: The semiconductor device package comprises a substrate 102 with a pre-formed die receiving cavity 105 and a terminal contact metal pad 112 formed within an upper surface. At lease a first die 104 is disposed within the die receiving cavity. A first dielectric layer 110 is formed on the first die and the substrate, and refilled into a gap between the first die and the substrate to absorb thermal mechanical stress there between. A first re-distribution layer (RDL) 114 is formed on the first dielectric layer and coupled to the first die. A second dielectric layer 116 is formed on the first RDL, and then a second die 120 is disposed on the second dielectric layer and surrounded by core pastes 124 having through holes 126 thereon. A second re-distribution layer (RDL) 128 is formed on the core pastes to fill the through holes, and then a third dielectric layer 130 is formed on the second RDL. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有良好CTE性能和收缩尺寸的半导体器件封装，提供具有令人满意的温度循环的板级可靠性。解决方案：半导体器件封装包括具有预成形的模具容纳腔105的基板102和形成在上表面内的端子接触金属焊盘112。至少第一模具104设置在模具接纳腔内。第一电介质层110形成在第一裸片和衬底上，并且重新填充到第一裸片和衬底之间的间隙中以吸收其间的热机械应力。第一再分配层（RDL）114形成在第一电介质层上并且耦合到第一裸片。在第一RDL上形成第二电介质层116，然后将第二裸片120设置在第二电介质层上并被其上具有通孔126的芯糊124包围。核心浆料上形成第二再分布层（RDL）128以填充通孔，然后在第二RDL上形成第三介电层130。版权所有（C）2009，JPO＆INPIT

84. 发明专利

JP4161359B2 Electronic circuit device and a method of manufacturing the same 有权
标题翻译：空值
公开(公告)号：JP4161359B2
公开(公告)日：2008-10-08
申请号：JP2001149121
申请日：2001-05-18
申请人：株式会社デンソー
发明人：昌弘山本 , 宏之酒井
IPC分类号： B22D17/00 , H01L21/60 , B22C9/06 , B22D17/22 , H01L23/04
CPC分类号： H01L2224/45 , H01L2224/45124 , H01L2224/48 , H01L2224/48091 , H01L2224/48472 , H01L2224/73265 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/157 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide an electronic circuit device which raises the bonding strength at the time when a defect in the surface of a bonding part is suppressed and an aluminum wire is bonded to the bonding part by a direct wire bonding method, and to provide a method of manufacturing the device. SOLUTION: In an electronic circuit device, a groove 30 is provided between a gate 40 used as a gate at the time of a casting of an aluminum case 10 and a bonding wire 20 for bonding an aluminum wire by a direct wire bonding method. Therefore, at the time of the start of a casting of an aluminum dicasting, splashes of a melted aluminum from the gate are blocked by the dam of a top mold to prevent the splashes from being adhered to a bonding part formation. Consequently, the bonding strength at the time when a defect in the surface of the bonding part 20 is suppressed and the aluminum wire is bonded to the bonding part 20 by the direct wire bonding method can be raised. Moreover, when an insulating board is made to secure on a board mounting surface 11 with a bonding agent or the like, the bonding agent can be prevented from flowing out on the periphery of the mounting surface 11 by the groove 30.
摘要翻译：要解决的问题：提供一种电子电路装置，其在接合部的表面的缺陷被抑制并且铝线通过直接引线接合方法接合到接合部时提高接合强度，并且提供提供一种制造该装置的方法。解决方案：在电子电路装置中，在铝壳10的铸造时用作浇口的浇口40和用于通过直接引线接合方法接合铝线的接合线20之间设置有槽30。因此，在铝铸造开始时，来自闸门的熔融铝的飞溅被上模的挡块阻挡，以防止飞溅粘附到接合部形成。因此，可以提高当接合部20的表面的缺陷被抑制并且铝线通过直接引线接合方法接合到接合部20时的接合强度。此外，当通过粘合剂等将绝缘板固定在板安装表面11上时，可以防止粘合剂通过槽30在安装表面11的周围流出。

85. 发明专利

JP2007095984A Semiconductor module 有权
标题翻译：半导体模块
公开(公告)号：JP2007095984A
公开(公告)日：2007-04-12
申请号：JP2005283260
申请日：2005-09-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMASHITA SHIRO , FUJIWARA SHINICHI , ISHIHARA SHOSAKU , YOSHINARI HIDETO
IPC分类号： H01L25/07 , H01L25/18
CPC分类号： H01L23/142 , H01L23/367 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/36 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/84 , H01L2224/04034 , H01L2224/04042 , H01L2224/05553 , H01L2224/0603 , H01L2224/29111 , H01L2224/32225 , H01L2224/40091 , H01L2224/40095 , H01L2224/40225 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73221 , H01L2224/73265 , H01L2224/77272 , H01L2224/83192 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/157 , H01L2924/30105 , H01L2924/351 , H01L2924/00 , H01L2924/01047 , H01L2924/00012 , H01L2224/37099
摘要： PROBLEM TO BE SOLVED: To prevent a lead from shifting in position from an electrode due to nonuniform solder wetting and solder reflow on the principal plane of the electrode joined with the principal plane of the lead, in a semiconductor module (power module) for electrically connecting a wire on a substrate with the electrode of a semiconductor chip mounted on the substrate on the principal plane of the lead formed like a plate or a film. SOLUTION: In the semiconductor module, a width of at least part of a region opposite to the semiconductor chip of the principal plane of the lead 6 employed in the module is widened to a width or larger of the electrode 8 formed on the principal plane of the semiconductor chip, and desirably, another region of the principal plane of the lead solder-connected with the wire formed on the substrate is divided in the extending direction of the lead 6. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了防止由于在与引线的主平面接合的电极的主平面上的不均匀的焊料润湿和焊料回流引起的位置从电极移位，在半导体模块（功率模块），用于将基板上的导线与安装在基板上的半导体芯片的电极连接，所述半导体芯片的电极形成为板状或薄膜状。解决方案：在半导体模块中，在模块中使用的引线6的主平面的半导体芯片的与半导体芯片相对的区域的至少一部分的宽度被加宽到形成在该模块上的电极8的宽度或更大并且希望地，与形成在基板上的线的铅焊料的主平面的另一区域沿导线6的延伸方向分开。（C）2007， JPO＆INPIT

86. 发明专利

JP2007095715A Sub-mount and its manufacturing method 有权
标题翻译：分装及其制造方法
公开(公告)号：JP2007095715A
公开(公告)日：2007-04-12
申请号：JP2005278958
申请日：2005-09-26
申请人： Dowa Holdings Co Ltd , Dowaホールディングス株式会社
发明人： NAKANO MASAYUKI , OSHIKA YOSHIKAZU
IPC分类号： H01L21/52 , H01L23/12
CPC分类号： C22C5/02 , B23K35/262 , B23K35/264 , B23K35/282 , B23K35/286 , B23K35/3006 , B23K35/3013 , B23K35/302 , B23K35/3033 , H01L21/50 , H01L23/3735 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/83 , H01L33/62 , H01L2224/04026 , H01L2224/291 , H01L2224/29109 , H01L2224/29111 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/73265 , H01L2224/83192 , H01L2224/83801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1301 , H01L2924/14 , H01L2924/157 , H01L2924/15724 , H01L2924/19107 , H01L2924/351 , H05K1/0306 , H05K1/111 , H05K3/3457 , H05K2201/09745 , Y02P70/611 , Y10T29/49393 , H01L2924/00014 , H01L2924/00015 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a sub-mount in which a rise of a melting point of a solder layer is prevented and a defect of a mounted semiconductor device is reduced and which has high bonding strength and to provide a manufacturing method of the sub-mount. SOLUTION: The sub-mount is provided with a sub-mount substrate 1, an electrode layer 2 formed on the sub-mount substrate and a solder layer 3 formed on the sub-mount substrate. The solder layer 3 is embedded in a window part 2A of the electrode layer, an outer peripheral part of the solder layer 3 is connected with the electrode layer 2 and the sub-mount 10 is constituted. The solder layer 3 has an overlap part 3A connected to an upper face 2A of the electrode layer. The rise of the melting point due to a change of a composition of the solder layer 3 is prevented without installing the solder barrier layer between the electrode layer 2 and the solder layer 3. The solder layer 3 and the semiconductor device can be bonded with high bonding strength, and the inexpensive sub-mount 10 can be supplied. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种防止焊料层的熔点升高并且半导体装置的缺陷被降低并且具有高的接合强度并且提供制造方法的子安装的子座。解决方案：子安装件设置有子安装基板1，形成在副安装基板上的电极层2和形成在副安装基板上的焊料层3。焊料层3嵌入电极层的窗部2A中，焊料层3的外周部与电极层2连接，构成副安装座10。焊料层3具有与电极层的上表面2A连接的重叠部分3A。阻止焊料层3的组成变化引起的熔点的上升，而不需要在电极层2和焊料层3之间设置阻焊层。焊料层3和半导体器件可以高粘合强度和廉价的副安装座10。版权所有（C）2007，JPO＆INPIT

87. 发明专利

JP2005288458A Joined body, semiconductor device, joining method and method for producing semiconductor device 审中-公开
标题翻译：接合体，半导体器件，用于制造半导体器件的接合方法和方法
公开(公告)号：JP2005288458A
公开(公告)日：2005-10-20
申请号：JP2004103984
申请日：2004-03-31
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKAHASHI TOSHIHIDE , MATSUMOTO KAZUTAKA , KOMATSU IZURU , TADAUCHI KIMIHIRO
IPC分类号： B23K1/19 , B23K1/00 , B23K35/00 , B23K35/26 , B23K101/40 , B32B15/01 , C22C5/02 , C22C5/06 , C22C13/00 , H01L21/52 , H01L21/60 , H05K3/34
CPC分类号： B23K35/262 , B23K35/007 , H01L24/29 , H01L24/80 , H01L2224/29111 , H01L2224/83101 , H01L2224/8381 , H01L2224/83825 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01057 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/01327 , H01L2924/0133 , H01L2924/014 , H01L2924/157 , H05K3/3463 , H01L2924/0105 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2924/00015
摘要： PROBLEM TO BE SOLVED: To provide a joined body capable of maintaining satisfactory mechanical strength even under high temperature conditions using joining materials which do not comprise lead at a high concentration. SOLUTION: The joined body 4 comprises a joining layer 3 of joining the first metal material 1 to be joined and the second metal material 2 to be joined composed of a material selected from the group consisting of copper, gold, silver, a gold-palladium-based alloy essentially consisting of gold and palladium and a silver-palladium based alloy essentially consisting of silver and palladium. Regarding the joining layer 3, at least one kind of phase selected from a solid solution phase comprising the constituting element(s) for the second metal material to be joined and tin and a tin phase, and a plurality of granular intermetallic compound phases comprising the constituting element(s) for the second metal material to be joined and tin are present in the cross-sectional fine structure thereof. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供即使在高温条件下也能够使用不含高浓度铅的接合材料，能够保持令人满意的机械强度的接合体。接合体4包括：接合层3，其接合待接合的第一金属材料1和被接合的第二金属材料2，所述第二金属材料2由选自铜，金，银，主要由金和钯组成的金 - 钯基合金和基本上由银和钯组成的银 - 钯基合金。关于接合层3，选自固溶相中的至少一种相，所述固溶相包括用于第二待接合金属材料的构成元素和锡和锡相，以及多个粒状金属间化合物相，其包含用于第二金属材料接合的构成元件和锡存在于其截面微细结构中。版权所有（C）2006，JPO＆NCIPI

88. 发明专利

JP2004079745A Interposer, manufacturing method therefor, electronic circuit device and manufacturing method therefor 审中-公开
公开(公告)号：JP2004079745A
公开(公告)日：2004-03-11
申请号：JP2002237396
申请日：2002-08-16
申请人： Sony Corp , ソニー株式会社
发明人： TAKAOKA YUJI
IPC分类号： H01L23/12 , H01L23/32
CPC分类号： H01L2224/16225 , H01L2924/01322 , H01L2924/10253 , H01L2924/15311 , H01L2924/157 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an interposer where shorting of a bump electrode and a semiconductor substrate can be prevented, a manufacturing method of the interposer, an electronic circuit device using the interposer, and to provide a manufacturing method of the device.
SOLUTION: A rear face of a silicon substrate 10 constituting the interposer 1 retreats so that a through conductive layer 12 protrudes from the rear face. Bump electrodes 30 which are connected to the respective through conductive layers 12 and are formed of solder are formed at tips of the through conductive layers 12 protruded from the rear face. Length L that the through conductive layer 12 protrudes from the rear face of the silicon substrate 10 is set to be about 1/5 to 1/10 of a diameter of the through conductive layer 12, for example, since a contact between the silicon substrate 10 and the bump electrode 30 due to deformation of the bump electrode 30 is prevented when a mounted substrate is subsequently connected to the through conductive layer 12 by the bump electrode 30.
COPYRIGHT: (C)2004,JPO

89. 发明专利

JP2017523587A メモリモジュール有权
公开(公告)号：JP2017523587A
公开(公告)日：2017-08-17
申请号：JP2016561023
申请日：2015-05-18
申请人：サンディスクテクノロジーズエルエルシー , サンディスクテクノロジーズエルエルシー
发明人：マニュエルアントニオディーアブレイユ , マニュエルアントニオディーアブレイユ
IPC分类号： H01L25/065 , G11C5/04 , H01L23/14 , H01L25/07 , H01L25/18
CPC分类号： H01L27/11551 , G11C5/025 , G11C5/04 , G11C5/06 , H01L23/3128 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0652 , H01L25/18 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/15192 , H01L2924/15311 , H01L2924/157
摘要：データ記憶デバイスは、3次元(3D)メモリ構成に配置された複数の記憶素子を含むメモリダイと、コントローラダイであって、メモリダイとコントローラダイとの隣接する表面間の複数の電気コンタクトを含むバスを介してメモリダイに結合されたコントローラダイとを含む。データ記憶デバイスにおいて実施される方法には、コントローラダイにおいて、メモリダイに記憶されるデータを受信することと、このデータを示すコードワードを生成することとが含まれる。このコードワードには、特定のビット数が含まれる。この方法には、コントローラダイからメモリダイに複数の電気コンタクトを介して信号を送信することも含まれる。複数の電気コンタクトには、コードワードの特定のビット数と少なくとも同数の電気コンタクトが含まれ、コードワードを示す信号は、コントローラダイからメモリダイに並行して送信される。【選択図】図1

90. 发明专利

JP2017143312A 磁気抵抗ランダムアクセスメモリ(MRAM)のためのスモールフォームファクタ磁気シールド审中-公开
公开(公告)号：JP2017143312A
公开(公告)日：2017-08-17
申请号：JP2017101618
申请日：2017-05-23
申请人：クアルコム,インコーポレイテッド
发明人：シーチュン・グ , ロンティアン・ジャン , ヴィディヤ・ラマチャンドラン , ドン・ウク・キム
IPC分类号： H01L21/8239 , H01L27/105 , H01L43/02 , H01L43/08 , H01L23/00
CPC分类号： H01L43/12 , H01L23/552 , H01L23/645 , H01L27/222 , H01L27/228 , H01L43/02 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/16227 , H01L23/3121 , H01L2924/0002 , H01L2924/1435 , H01L2924/157 , H01L2924/15788 , H01L2924/3025
摘要：【課題】磁気抵抗ランダムアクセスメモリ(MRAM)のためのスモールフォームファクタ磁気シールドを提供する。【解決手段】いくつかの実装形態は、いくつかの磁気抵抗ランダムアクセスメモリ(MRAM)セルを含むMRAMセルアレイを含むダイを提供する。ダイはまた、MRAMセルアレイの上に配置された第1の強磁性層と、MRAMセルアレイの下に配置された第2の強磁性層と、少なくとも1つのMRAMセルの周りに配置されたいくつかのビアとを含む。ビアは強磁性材料を含む。いくつかの実装形態では、第1の強磁性層、第2の強磁性層、およびいくつかのビアが、MRAMセルアレイのための磁気シールドを画定する。MRAMセルは、磁気トンネル接合(MTJ)を含み得る。いくつかの実装形態では、いくつかのビアは、ダイの少なくとも金属層および誘電体層を横断する。いくつかの実装形態では、ビアは基板貫通ビアである。いくつかの実装形態では、強磁性材料は、高い透磁率および高い飽和磁束密度を有する。【選択図】図5

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