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81. 发明专利

JPH03250667A MOS FIELD-EFFECT TRANSISTOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH03250667A
公开(公告)日：1991-11-08
申请号：JP25665590
申请日：1990-09-25
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKUMURA YOSHIKI
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336
摘要： PURPOSE:To prevent occurrence of punch-through as well as to realize a well without a residual stress by providing a first well and a second well of second conductivity type formed to enclose one source/drain region and the other source/drain region of first conductivity type, which are formed separately on both sides of a gate on the main surface of a semiconductor substrate. CONSTITUTION:A first well 17 and a second well 18 being an N-type impurity region are formed on the main surface of a semiconductor substrate 1 on both sides of a gate 2. The wells 17, 18 have parts 17a, 18a vertically overlapping the gate 2. A source region 3 being a P-type impurity diffusion layer is formed inside the well 17, while a drain region 4 being a P-type impurity diffusion region is formed inside the well 18. Thus a depletion layer in the vicinity of the drain 4 does not spread to the source region 3 so that punch-through can be effectively prevented. Since the wells 17, 18 are small wells which enclose only the source/drain regions 3, 4, thermal treatment at a high temperature is not necessary resulting in no distortion due to thermal stress.

82. 发明专利

JPH03204940A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03204940A
公开(公告)日：1991-09-06
申请号：JP17921390
申请日：1990-07-05
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKUMURA YOSHIKI
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/36 , H01L29/78
摘要： PURPOSE:To form respectively a high potential barrier at both ends of a channel region and to improve source/drain breakdown strengths by a method wherein the formation of ion-implanted layers for controlling a threshold voltage is performed by an obliquely rotating ion implantation method using a transfer gate electrode as a mask. CONSTITUTION:Boron ions which are P-type impurity ions identical with those in a semiconductor substrate 1 are obliquely implanted in the whole surface of the substrate 1 from the direction at a prescribed angle of inclination with respect to the direction normal to the substrate surface. Simultaneously with this, the substrate 1 is rotated centering around the normal of the center of a transfer gate electrode 5. By this obliquely rotational ion implantation method, P-type ion-implanted layers 4 for threshold voltage control use are formed using the electrode as a mask. It is desirable to set the angle of inclination for the ion implantation at 15 deg. or larger and 60 deg. or smaller and the ion implantation is normally performed at about 30 deg. or larger and about 45 deg. or smaller. Thereby, the concentration distribution of an impurity subsequent to diffusion can be made high remarkedly in the vicinities of a source and a drain at both ends of a channel region compared to that of the impurity in the vicinity of the center of the channel region.

83. 发明专利

JPH02168626A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH02168626A
公开(公告)日：1990-06-28
申请号：JP16757789
申请日：1989-06-29
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKUMURA YOSHIKI , NAGATOMO MASAO , OGAWA IKUO , MATSUKAWA TAKAYUKI , GENJIYOU HIDEKI , HACHISUGA ATSUSHI
IPC分类号： H01L23/52 , H01L21/3205
摘要： PURPOSE:To obtain a highly reliable wiring structure excellent in electric conduction by constituting at least one out of a plurality of wiring layers as a structure wherein a barrier metal layer, an aluminum alloy layer, and an antireflection film are laminated in said order from a semiconductor substrate side. CONSTITUTION:An auxiliary word line 12a is connected with a lower layer word line 10a, on a specified field oxide film 22. The auxiliary word line 12a is constituted as a three layer lamination structure wherein a barrier metal layer 6, an aluminum alloy layer 7, and an anti reflection film 8 are stacked in order from the lower layer. At the contact part between the auxiliary word line 12a and the word line 10a, the auxiliary word line 12a is constituted as a four layer structure wherein a silicide layer 20, a barrier metal layer 6, an aluminum alloy layer 7 and an antireflection film 8 are stacked in order from the lower layer. In this case, the antireflection film 8 prevents exposure light from scattering at the time of patterning the wiring layer, thereby realizing the microstructure of the wiring pattern. The barrier metal layer 6 at the contact part improve contact characteristics. By this set-up, the reliability of the wiring layer is improved.

84. 发明专利

JPH02117152A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02117152A
公开(公告)日：1990-05-01
申请号：JP27120288
申请日：1988-10-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： WAKAMIYA WATARU , OKUMURA YOSHIKI , OGAWA IKUO , OZAKI KOJI , MATSUKAWA TAKAYUKI , NAGATOMO MASAO
IPC分类号： H01L21/302 , H01L21/28 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To contrive a proper etching process by etching insulating film by the use of a mask corresponding to the depth of a contact hole. CONSTITUTION:A photomask 11a is provided on the upper side of a resist 13a and only a place of opening 12a is formed on the photomask and its opening corresponds to a contact hole. Once irradiating, an opening 14a is formed. Then the contact hole is formed by etching an insulating film 10 that is exposed to the opening 14a with a RIE process. Then, after removing the resist 13a, a resist 13b is applied newly. A photomask 11b is provided and an opening 12b is formed at a position corresponding to the contact hole. Further, an opening 14b is formed with irradiation. Then a contact hole T1 is formed by etching. Even if etching thicknesses of the insulating film 10 are different, etching time in response to the thickness is secured. Consequently, no overetching, insufficient etching and the like take place in this manufacturing process.

85. 发明专利

JPH02100297A GENERATION METHOD FOR X-RAY OF LASER EXCITATION TYPE 失效
公开(公告)号：JPH02100297A
公开(公告)日：1990-04-12
申请号：JP25415088
申请日：1988-10-07
申请人： MITSUBISHI ELECTRIC CORP
发明人： CHIBA AKIRA , OKUMURA YOSHIKI
IPC分类号： H05G2/00 , H01L21/027 , H01S3/094 , H01S4/00
摘要： PURPOSE:To prevent a heat explosion from taking place due to local heating of a buret-shaped target which is smaller than the spot diameter of a laser beam, by irradiating the target with the laser beam so that it produces an X-ray. CONSTITUTION:A laser beam 12 is initially introduced into a vacuum chamber 11 so that the chamber is irradiated therewith, then a buret-shaped target 13 which is smaller than the spot diameter of the laser beam is caused to fall freely within the area irradiated with the laser beam 12 inside the vacuum chamber 11. The buret-shaped target 13, which is thus inserted into the vacuum chamber 11, is then irradiated with the short-pulse laser beam 12 having high power density, within the portion where it intersects with the area irradiated with the laser beam 12, so that it is rapidly heated and therefore vaporized and also converted into plasma to generate an X-ray 15. A heat explosion can thus be prevented from taking place due to local heating of the target.

86. 发明专利

JPH0279467A SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0279467A
公开(公告)日：1990-03-20
申请号：JP23081388
申请日：1988-09-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： GENJIYOU HIDEKI , MATSUKAWA TAKAYUKI , NAGATOMO MASAO , OGAWA IKUO , OKUMURA YOSHIKI , HACHISUGA ATSUSHI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108
摘要： PURPOSE:To prevent influx of electric charges generated by alpha-beam into a memory cell in better performance by including high concentration impurities in a first electroconductive type impurity layer, which is to become a barrier layer, and forming a certain distance apart from the boundary of a second electroconductive type impurity region constituting a memory element. CONSTITUTION:The impurity concentration of a P -buried layer 40 concerned to work as a barrier layer is controlled to 10 -10 cm , with a concentration slope of 10-10 cm continued to the region of P-type well layer having an impurity concentration of 10 cm . This P -buried-layer 40 is situated 1.0-2.0mum apart from the surface of silicon base board, with peak value of the impurity concentration lying preferably apart 1.5mum in the order of magnitude 10 cm . When alpha-beam is incident on the P-type well layer 2 as a memory forming region where P -buried layer 40 with controlled impurity concentration and position of forming, most of electron-positive hole couples produced in the silicon base board by irradiation of alpha-beam are hindered by the P -buried layer 40. This precludes influx into N-type impurity dispersive regions 61, 62, which constitute memory cell.

87. 发明专利

JPH0279466A MANUFACTURE OF SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0279466A
公开(公告)日：1990-03-20
申请号：JP23081688
申请日：1988-09-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： GENJIYOU HIDEKI , OGAWA IKUO , MATSUKAWA TAKAYUKI , NAGATOMO MASAO , OKUMURA YOSHIKI , HACHISUGA ATSUSHI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To prevent generation of residues in the boundary region between well layers by performing removal so that the main surface of a first semiconductor region is exposed in the condition trench is filled with a filling material, when the trench formed in the first semiconductor region is to be filled with filler, and then removing the remaining filling material in the condition that trench part and the exposed main surface of the first semiconductor region are masked. CONSTITUTION:An embedded deposit layer 16a formed over the whole surface of a silicon base board is removed by means of etching-back until the deposit layer fills only the trench concerned and keeps the same level as the surface of the region of P-type well layer 2. In this etching process, resist film 14 is formed selectively only on the region of P-type well layer 2 where trench is formed. Further, etching of the embedded deposit layer 16a is conducted using this resist film as a mask. Accordingly only trenches in the deposit layer 16a are filled, and an embedded separate layer 16 is accomplished. At this time, no residues of embedded deposit layer 16a are produced at level difference part formed between P-type and N-type well layers 2, 3.

88. 发明专利

JPH01147843A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01147843A
公开(公告)日：1989-06-09
申请号：JP30805887
申请日：1987-12-03
申请人： MITSUBISHI ELECTRIC CORP
发明人： OZAKI KOJI , OGAWA IKUO , OKUMURA YOSHIKI , NAGATOMO MASAO , WAKAMIYA WATARU
IPC分类号： H01L21/3205 , H01L21/822 , H01L23/522 , H01L23/532 , H01L27/04 , H01L27/108
摘要： PURPOSE:To provide good uniformity of the thickness of wirings and to wire with high reliability by depositing polysilicon on a contact, burying it by etching back, and wiring with a second conductive material. CONSTITUTION:After an interlayer insulating film 4 is patterned, a first conductive film 5 is initially deposited. The film 4 is etched back to the position indicated by the film 5. A diffused layer of a substrate is not exposed on the surface at all by the etching-back. A second conductive material 6 is deposited, and patterned. Then, the film 5 is ohmically connected to the material 6. Thus, good uniformity of the thickness of wirings is obtained, the disconnection trouble ratio due to the migration of the wirings is reduced, and wirings of high reliability is performed.

89. 发明专利

JPH01146353A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01146353A
公开(公告)日：1989-06-08
申请号：JP30612287
申请日：1987-12-02
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKUMURA YOSHIKI
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/41
摘要： PURPOSE:To obtain a semiconductor memory device wherein connection parts of bit lines and a transistor are improved, and high degree integration and high density mounting are enabled, by providing a first impurity region and a first conductor, the former being formed on the side wall of a first trench and connected to a transistor, the latter being formed in the inside of the first trench and in contact with the first impurity region. CONSTITUTION:A semiconductor memory device containing a transistor and a capacitor connected to the transistor is provided with a semiconductor substrate 3, a first impurity region 2, and a first conductor 1. The semiconductor substrate 3 has a main surface and a first trench 26 formed on the main surface. The first trench 26 has a side wall. The first impurity layer 2 is formed on the side wall of the first trench 26, and connected to the above transistor. The first conductor 1 is formed in the inside of the first trench, and in contact with the first impurity region. For example, the source and the drain regions of the above transistor are formed on the main surface of the semiconductor substrate 3. Further, on the main surface, a second trench 18 having a side wall is formed, in the inside of which the above capacitor is formed.

90. 发明专利

JPH01123416A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01123416A
公开(公告)日：1989-05-16
申请号：JP28162287
申请日：1987-11-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： NAGATOMO MASAO , MATSUKAWA TAKAYUKI , OZAKI KOJI , WAKAMIYA WATARU , OKUMURA YOSHIKI , OGAWA IKUO
IPC分类号： H01L21/22 , H01L21/8238 , H01L27/08 , H01L27/092
摘要： PURPOSE:To form two semiconductor layers having mutually opposite conductivity type active regions without overlapping, by performing doping with impurities when a plurality of semiconductor layers are formed in region, which is at a specified distance from a boundary line between the intended two semiconductor layers. CONSTITUTION:An oxide film 2 and a nitride film 3 are sequentially formed on a silicon substrate 1. Etching is performed with a resist mask 4 as a mask. At this time, the surface region of the substrate 1 is exposed from a boundary line, which is separated from an intended boundary line X between an N-type well layer and a P-type well layer, by a specified distance (d). N-type impurity ions are implanted, and an N-type ion implanted layer 5 is formed. When heat treatment is performed, the N-type impurities, which are implanted into the substrate 1, are diffused in the lateral direction, and an N-type well layer 51 is formed. P-type impurity ions are implanted, and a P-type ion implanted layer 7 is formed. When heat treatment is performed, the P-type impurities, which are implanted into the substrate 1, are diffused in the lateral direction, and a P-type well layer 71 is formed.

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