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81. 发明专利

JPH0418733A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0418733A
公开(公告)日：1992-01-22
申请号：JP12110790
申请日：1990-05-14
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAMAOKI YOICHI , SHIBA TAKEO , SAGARA KAZUHIKO , KURE TOKUO , NAKAMURA TORU , OGIWARA ITARU
IPC分类号： H01L29/73 , H01L21/31 , H01L21/331 , H01L21/76 , H01L29/732
摘要： PURPOSE:To manufacture the title semiconductor device capable of flattening the upper part of trenches by a method wherein the insulation separating trenches are formed between elements on a substrate and after forming buried material on the whole surface and etching away the material previously formed around projection parts only, the buried material on the whole surface is further etched away. CONSTITUTION:An n type buried layer 2 for collector is formed on a P type substrate 1 to form an Si epitaxial growing layer 3 on the film 2 and then an SiO2 film 4, an Si3O4 film 5 and another SiO2 film 6 are successively formed. After halfway etching away the epitaxial growing layer 3 using the three layer film as a mask to form the SiO2 film by thermal process, another Si3N4 film 7 is deposited on the whole surface to be left only on the sidewall of projection parts by etching away process. Next, Si trenches 8 for element separation are formed further to form the other SiO2 film 9. After removing the Si3N4 film 7, the other Si3N4 film 10 is formed on the whole surface to form a polycrystal silicon film 11. Next, after the whole surface is coated with a photoresist film 13 so as to be flattened, the film 13 is removed until the projection part of the film 11 is exposed and furthermore after removing the film 13, the film 11 is etched away until the surface of the trenches 8 is exposed.

82. 发明专利

JPH03174733A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03174733A
公开(公告)日：1991-07-29
申请号：JP31337289
申请日：1989-12-04
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , KAWAMOTO YOSHIFUMI , KITSUKAWA GORO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/732
摘要： PURPOSE:To achieve a high current gain even in a smaller device by providing a perforated insulating film on a central portion of an active region of a substrate, and an emitter region on the active region outside the insulating film. CONSTITUTION:An insulating film 12 with a hole is provided on a central portion of the active region of a substrate 1. An emitter region 5 is formed in an active region outside the central portion. In the hole of the insulating film is formed a base contact 14 that is connected with the substrate 1. An insulating film is formed at an upper portion of the base contact, and another insulating film around the base contact. An emitter contact 13 is in contact with an emitter region through these insulating films. This structure increases the emitter area in the active region. In addition, the emitter area ratio is maintained constant even in a smaller device, thus preventing the decrease in current amplification factor.

83. 发明专利

JPH0362568A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0362568A
公开(公告)日：1991-03-18
申请号：JP19656989
申请日：1989-07-31
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , ITO KIYOO , KITSUKAWA GORO , KAWAMOTO YOSHIFUMI , KAWAJIRI YOSHIKI
IPC分类号： H01L21/8242 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/108
摘要： PURPOSE:To obtain an IC of high performance and high integration degree by a method wherein, after the emitter of bipolar transistor is formed, the source and drain of a MOS transistor is formed, the depths of emitters xjE(BiP) and xj(MOS) are inverted, and the following relation is obtaind; xj(MOS)

84. 发明专利

JPH02237152A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH02237152A
公开(公告)日：1990-09-19
申请号：JP5643289
申请日：1989-03-10
申请人： HITACHI LTD
发明人： SHIBA TAKEO , SAGARA KAZUHIKO , TAMAOKI YOICHI , HONMA NORIYUKI , NAKAZATO KAZUO , ONOUCHI YUKIHIRO , NAKAMURA TORU
IPC分类号： H01L27/06 , H01L21/8222 , H01L21/8229 , H01L27/102
摘要： PURPOSE:To reduce an area of a memory cell by a method wherein a clamping diode of the memory cell is formed of polycrystalline Si and is piled up on a transistor and a resistance element. CONSTITUTION:A first polycrystalline Si film electrode 10 into which impurities whose conductivity type is identical to that of a collector electrode have been injected is deposited on the collector electrode; in addition, a second polycrystalline Si film 13 into which impurities whose conductivity type or concentration is different from that of the impurities have been injected and which is composed of a single layer or many layers and a metal electrode 11 are formed on it. A diode is formed of the first and second polycrystalline Si films 10, 13 or of the second polycrystalline Si film 13 and the metal electrode 11. That is to say, an SBD(Schottky barrier diode) formed of the metal electrode 11 and the n-type polycrystalline Si film 13 is placed on a region of a collector 9 of a transistor for retention use and a high resistance 5. Thereby, since a region to form the SBD is not required, an area of a memory cell can be reduced.

85. 发明专利

JPH01241168A BIPOLAR TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01241168A
公开(公告)日：1989-09-26
申请号：JP6739988
申请日：1988-03-23
申请人： HITACHI LTD
发明人： KONDO MASAO , SAGARA KAZUHIKO , TAMAOKI YOICHI , MIYAO MASANOBU
IPC分类号： H01L29/73 , H01L21/331 , H01L21/76 , H01L29/72 , H01L29/732
摘要： PURPOSE:To reduce capacitance between a collector and a substrate down to less than one-tenth, by embedding metals or a metal silicide and an insulating film below the n type buried layer of a bipolar transistor. CONSTITUTION:An insulation layer 2 is deposited on a polished principal plane 1 and a barrier metal or a metal silicide film 3 which prevents a metal film and a metal from changing into a silicide is deposited on the above insulating layer and further, an amorphous Si film or a polycrystal Si film is deposited on the above metal film or the metal as binders. After that, both an Si substrate A where an n type polycrystal layer 4 activated by ion implantation of As is formed and an Si substrate B which has an n-type principal plane are joined directly by bonding one polished face to the other one after making two polished faces face each other, thereby heating them at a temperature 800 deg.C or more. Subsequently, layers on the surface of the substrate B are etched from the rear so that only an n-type layer 5 on the surface may remain and the substrate B allows an n-type epitaxial layer to grow. In this way, the insulating film, the metal or a metal silicide are embedded in a single crystal Si. Thus, the capacitance of a collector substrate can be almost zero.

86. 发明专利

JPS649654A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS649654A
公开(公告)日：1989-01-12
申请号：JP16391787
申请日：1987-07-02
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , SHIMOHIGASHI KATSUHIRO , NAKAMURA TORU , HONMA NORIYUKI , KIMURA KATSUTAKA , NANBA MITSUO , KONDO MASAO , NAKAZATO KAZUO
IPC分类号： H01L27/10 , H01L21/8229 , H01L21/8242 , H01L27/102 , H01L27/108
摘要： PURPOSE:To obtain a memory cell structure to be used for an alpha-ray resisting reinforced dynamic RAM by a method wherein a transistor is constituted by a transistor which can be operated in two directions, and a charge accumulation layer is provided on the surface of a semiconductor device. CONSTITUTION:The transistor 100 is a SICOS type bipolar transistor having the structure wherein a base electrode is picked out by a polycrystalline silicon film 12, and a charge accumulation layer 101, consisting of a polycrystalline silicon film 13, a silicon dioxide film 10 and an electrode 29, is provided directly above said transistor 100. Also, the emitter of the transistor 100 and the charge accumulation layer 101 are connected. As the charge accumulation layer 101 is formed directly above the transistor 100, elements can be formed in a highly integrated manner. Also, as the charge accumulation layer 101 is provided on the element surface, the information breakdown generated by the external noise of electrons, holes and the like caused by alpha-rays can be prevented.

87. 发明专利

JPS6379373A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6379373A
公开(公告)日：1988-04-09
申请号：JP22352586
申请日：1986-09-24
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , TAMAOKI YOICHI , HONMA NORIYUKI , NAKAMURA TORU
IPC分类号： G11C11/411 , H01L21/8229 , H01L27/102
摘要： PURPOSE:To provide alpha-ray resisting strength and to implement a high integration density of 64kbits or more, by providing a Schottky barrier diode and other semiconductor elements directly on a bipolar transistor. CONSTITUTION:SiO29 is provided in a part of polycrystalline Si17. Then, a P-type diffusion layer 5, a P type diffusion layer 6 and an N type diffusion layer 4 are provided. Thus an emitter region and a base region are formed. Then a polycrystalline Si layer is deposited on the surface of an element. Thereafter, ions are implanted, and an N-type polycrystalline Si region 12 and an N type polycrystalline Si region 13 are formed. Then, SiO27 is provided on the surface of the element. A hole is provided at a part of the SiO27, and an N type diffusion layer 14 and a silicide layer are formed.

88. 发明专利

JPS6364364A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6364364A
公开(公告)日：1988-03-22
申请号：JP20785386
申请日：1986-09-05
申请人： HITACHI LTD
发明人： SAGARA KAZUHIKO , TAMAOKI YOICHI , NAKAMURA TORU , KETSUSAKO MITSUNORI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
摘要： PURPOSE:To change the ratio of the areas of an emitter and a base in an active region arbitrarily, and to simplify a process largely by forming an emitter and base regions into a semiconductor single crystal substrate apart from an Si substrate. CONSTITUTION:An N type buried layer 2, an N type epitaxial layer 3 and silicon oxide 4 are shaped onto a P-type Si substrate 1. Amorphous-silicon is deposited on the whole element, and changed into single crystal silicon 13 through heat treatment. An angle theta is brought to 75 deg. or less at that time. A P-type diffusion layer 6 is worked, silicon dioxide 5 is deposited, and an opening section is formed. Arsenic is deposited in the hole to shape an N type diffusion layer, and N type polycrystalline silicon 9 is deposited. An opening section 14 is formed, and a P type diffusion layer 7 and successively an emitter electrode 10, a base electrode 11 and a collector electrode 12 are shaped.

89. 发明专利

JPS6262556A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6262556A
公开(公告)日：1987-03-19
申请号：JP20152885
申请日：1985-09-13
申请人： HITACHI LTD
发明人： TAMAOKI YOICHI , SAGARA KAZUHIKO , IKEDA SEIJI , NAKAMURA TORU , HAYASHIDA TETSUYA
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
摘要： PURPOSE:To reduce irregular characteristics by directly contacting an Si3N4 film with Si at the end of Si3N4/SiO2 film to prevent bird beaks from extending due to diffusion of oxygen through the SiO2 film of a lower mask layer at separate oxidation time. CONSTITUTION:An SiO2 film 6, an Si3N4 film 5, and an SiO2 film 4 of portions except an element forming region are etched, an Si epitaxial layer 3 is etched, thermally oxidized to form an SiO2 film 7 on the surface of a groove, and the film 7 remains on the side of the groove. Then, after the Si is lightly etched, an Si3N4 film 8 is coated, again etched to allow the film 8 to remain on the side of the groove. Here, the size of the portion 9 in which the film 8 is directly coated on the silicon is important, and the size is controlled by altering the slope of the groove and the etching amount in the light Si etching. Then, after an SiO2 film 10 is formed in the groove by thermal oxidation, the film 8 is removed, the thin film 7 of thin insolar portion is selectively removed, and a polycrystalline silicon film 11 is then formed.

90. 发明专利

JPS61252664A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS61252664A
公开(公告)日：1986-11-10
申请号：JP9360985
申请日：1985-05-02
申请人： HITACHI LTD
发明人： TAMAOKI YOICHI , SAGARA KAZUHIKO , SAKAI YOSHIO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
摘要： PURPOSE:To improve integration degree, by taking out a base contact from the oblique upper part of a base region by using polycrystalline silicon. CONSTITUTION:An embedded layer 2 is diffused in an Si substrate 1. An Si epitaxial growing layer 3 is formed on the layer 2. Four layers of an SiO2 film 4, an Si3N4 film 5, an SiO2 film 6 and an Si3N4 film 7 are formed. Then, a resist pattern 8 is formed, and the film 7 and the film 6 are etched. The film 6 is further side-etched. With the Photoresist 8 as a mask, the film 5 and the film 4 are vertically machined by dry etching, and the resist is removed. A part of the film 3 is etched. Thereafter, an SiO2 film 9 is formed by selective oxidation. After the film 5 is etched, the SiO2 film 7 is etched. Then a slant surface 10 of Si is exposed. Thereafter, a poly Si film 11 is deposited on the surface. A hole 12 is provided, and an intrinsic base region 14 is formed. Then, the poly Si is oxidized, and an SiO2 film 15 is formed. A hole is provided through the Si3N4 film 5 and the SiO2 film 4, and an emitter diffused layer is formed. An emitter electrode 17, a base electrode 18 and a collector electrode are formed. Thus, the integration degree is improved, and decrease in stray capacity can be realized.

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