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81. 发明专利

JPH01213042A MULTIPLEXING SYSTEM 失效
公开(公告)号：JPH01213042A
公开(公告)日：1989-08-25
申请号：JP3928388
申请日：1988-02-22
申请人： FUJITSU LTD
发明人： YAMASHITA HARUO , OTSUKA TOMOYUKI , KONDO RYUICHI , KAWAI MASAAKI
IPC分类号： H04J3/00
摘要： PURPOSE:To simplify a high-speed signal processing circuit by multiplexing parallel scramble output and (k) bit data at every CH, multiplexing the signal of the whole CH after prescribed delay processing and enabling the processing of scramble or the like at a low-frequency stage to be executed. CONSTITUTION:The analogue signals Ai1-AiN are digitized by A/D conversion circuits 101-10N and scrambled in parallel by scrambles 111-11N. The PN signal of an M-system which is shifted only (n+k) at every clock by each scrambler and a value in a state that it is shifted only (n+k) bit for the adjacent scrambler is set to initial value setting circuits 121-12N. The parallel scramble output and the (k) bit data column are multiplexed at every channel(CH) by multiplexing circuits 131-13N. The channel is delayed so as to be delayed by (k) bit from the adjacent CH by a delay circuit 14 by inputting the multiplexing the output at every CH. The signal of the whole CH of the circuit 14 which are processed like that are multiplexed by a multiplexing circuit 15.

82. 发明专利

JPS6478012A PHASE SHIFTING CIRCUIT 失效
公开(公告)号：JPS6478012A
公开(公告)日：1989-03-23
申请号：JP23366587
申请日：1987-09-19
申请人： FUJITSU LTD
发明人： KAWAI MASAAKI , WATABE HISAKO
IPC分类号： H03H7/20 , H03H11/20
摘要： PURPOSE:To obtain a phase shifting circuit of 0 deg.-360 deg. consisting of a semiconductor device possible to be integrated by generating an output signal in which phase shift proportional to weight is added on an input signal by a weighting control signal. CONSTITUTION:A separation part 31 generates a 0-phase separation signal Sso and pi/2-phase separation signal Ss90 having a phase difference of 90 deg. with each other by receiving the input signal Sin, and a distribution part 32 generates a 0-phase distribution signal Sdo, a pi/2-phase distribution signal Sd90, and a pi-phase distribution signal Sd180 having the phase differences of 90 deg. and 180 deg. with each other. A weighting synthetic part 33 separates the signal to plural kinds of phase shift signals having respective phase range individually, and also, performs the synthesis of the signals after weighting an amplitude component, respectively, and the phase shift circuit 30 decides the weighting by receiving the weighting control signal Sw from the outside, and the quantity of phase shift of an Sout for the Sin by the weighting. In such a way, since the quantity of the phase shift can be controlled by an arithmetic operation, no variable L or no varable C is interposed, and it is possible to perform the phase shift extending over 0 deg.-360 deg. only by the semiconductor device.

83. 发明专利

JPS6345914A VARIABLE DELAY CIRCUIT 失效
公开(公告)号：JPS6345914A
公开(公告)日：1988-02-26
申请号：JP18839686
申请日：1986-08-13
申请人： FUJITSU LTD
发明人： KITASAGAMI HIROO , KAWAI MASAAKI , AMAMIYA IZUMI
IPC分类号： H03H11/26
摘要： PURPOSE:To attain an optimum phase while adjusting the phase of a clock signal in an integrated logic circuit of high speed operation or the like by adjusting a current of a constant current source so as to vary the emitter- collector voltage of transistors (TRs) connected to the constant current source thereby varying the delay time between the input and output. CONSTITUTION:Bases of TRs 11,12 are connected to an input terminal IN, collectors are connected to an output terminal OUT and emitters are connected in common and to a collector of a TR 13 forming a constant current source. In adjusting a variable resistor 20 to adjust a current flowing to a TR 17, the current value flowing to the TR 13 forming the constant current source is set. The variable resistor 20 is connected to a terminal of the integrated circuit, allowing to adjust the delay time of the variable delay circuit comprising the TRs 11, 12 and 13 or the like subject to circuit integration externally and optionally. Thus, the minute adjustment of the delay time is facilitated and if the delay time is deficient by one stage, the desired delay time is obtained easily through multi-stage connection.

84. 发明专利

JPS631211A INTERFACE CIRCUIT 失效
公开(公告)号：JPS631211A
公开(公告)日：1988-01-06
申请号：JP14427886
申请日：1986-06-20
申请人： FUJITSU LTD
发明人： HAMANO HIROSHI , YAMAGUCHI KAZUO , KITASAGAMI HIROO , AMAMIYA IZUMI , KAWAI MASAAKI
IPC分类号： H03K19/0175 , H03K19/00 , H04L25/02
摘要： PURPOSE:To prevent deterioration the transmission characteristics caused by the stray capacity of a transmission line by using a current drive circuit of a high output impedance to form an output circuit of the transmission side and a base earth circuit of a low input impedance to form an input circuit of the reception circuit. CONSTITUTION:An output circuit 1 of the transmission side is formed with a current drive circuit 1A of a high output impedance together with an input circuit 2 of the reception side formed with a base earth circuit respectively. The emitter of a transistor TR24A forming the circuit 2 is connected to the circuit 1 via a signal line 100. In such a constitution, an interface circuit using the collector of the TR2A as an output is obtained. The circuit 1 supplies the signal produced by the current drive to the base earth circuit. This base earth circuit has a low input impedance in terms of AC that is equal to the emitter resistance value. Then the stray capacity C eliminates substantially the electrical circuit connection with a load resistance 23 for transmission of signals. Thus the signal transmission characteristics are never deteriorated by the increase of the stray capacity despite the stray capacity added to a signal line.

85. 发明专利

JP2010039409A Optical module, optical control method by optical module, optical switch and optical switching method 有权
标题翻译：光学模块，光学模块光学控制方法，光学开关和光学切换方法
公开(公告)号：JP2010039409A
公开(公告)日：2010-02-18
申请号：JP2008205070
申请日：2008-08-08
申请人： Fujitsu Ltd , Univ Of Tokyo , 国立大学法人東京大学 , 富士通株式会社
发明人： YAMASHITA SHINJI , YAMAMOTO TAKESHI , KAWAI MASAAKI , FUJITA HIROYUKI
IPC分类号： G02B26/08 , G02B26/02
CPC分类号： G02B26/0825 , G02B6/352 , G02B26/06
摘要： PROBLEM TO BE SOLVED: To suppress an absolute decrease in the intensity of light, and to output stable output light. SOLUTION: An optical module 10 includes: a mirror 11 which reflects input light La and which outputs output light Lb; and a mirror control section (in Fig.1, a glass substrate 12 and a substrate 13 having electrodes 12a and 13a, respectively) which is opposite to the mirror 11 and controls, at the time of the input light La being reflected from a reflecting surface of the mirror 11, the reflecting surface by distorting the reflecting surface according to a voltage applied to the mirror 11 so as to output the output light Lb the optical coupling characteristic of which is changed. By using this optical module, the optical coupling characteristic of the output light Lb is changed. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：抑制光强度的绝对降低，输出稳定的输出光。解决方案：光学模块10包括：反射输入光La并输出输出光Lb的反射镜11; 和反射镜控制部分（在图1中，玻璃基板12和分别具有电极12a和13a的基板13），其与反射镜11相反，并且在输入光La被反射时被控制反射镜11的表面，通过根据施加到反射镜11的电压使反射表面变形从而输出其光耦合特性被改变的输出光Lb来反射反射表面。通过使用该光学模块，输出光Lb的光耦合特性发生变化。版权所有（C）2010，JPO＆INPIT

86. 发明专利

JPH0851416A CLOCK SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH0851416A
公开(公告)日：1996-02-20
申请号：JP18731694
申请日：1994-08-09
申请人： FUJITSU LTD
发明人： MATSUOKA NAOKI , TOMONAGA HIROSHI , KAWAI MASAAKI
IPC分类号： H04L7/02 , H04L12/28 , H04Q3/00
摘要： PURPOSE:To constitute a clock synchronizing circuit as compact as possible without requiring a high speed input clock in respect to a clock synchronizing circuit especially for a cross point ATM switch or the like. CONSTITUTION:The clock synchronizing circuit is provided with a 1st phase generating means 100 for receiving an input signal synchronized with input data and outputting plural delay signals having phases different from that of the input signal, an optimum phase detecting means 200 for comparing the phase of each delay signal with that of a prescribed clock signal and detecting a delay signal having a phase difference to be surely detected by the clock signal, a 2nd phase generating means 300 for receiving the input data and generating plural delay data having the same phase difference as that of the delay signal concerned, and a synchronizing data selecting means 400 for selecting delay data having the same phase difference as that of the delay signal detected by the means 200 from the input data.

87. 发明专利

JPH07261981A FIFO CONTROL CIRCUIT 失效
公开(公告)号：JPH07261981A
公开(公告)日：1995-10-13
申请号：JP7412394
申请日：1994-03-18
申请人： FUJITSU LTD
发明人： OMURA TETSUYA , KAWAI MASAAKI , TAKIZAWA YUJI
IPC分类号： G11C7/00 , G06F5/06 , G06F5/10
摘要： PURPOSE:To provide a FIFO control circuit of circuit constitution for reducing the cost, relating to FIFO control circuit using a two-port RAM. CONSTITUTION:This circuit is provided with the two-port RAM 1 provided with the input port of write data and the output port of read data, a read side counter circuit 3 for generating a write address and write enable to the two-port RAM 1 and a read side counter circuit 5 for generating a read address to the two-port RAM 1. The write side counter circuit 3 and the read side counter circuit 5 respectively input trigger signals and generate the write address, the write enable and the read address.

88. 发明专利

JPH0722927A CLOCK SWITCHING CIRCUIT 失效
公开(公告)号：JPH0722927A
公开(公告)日：1995-01-24
申请号：JP15023793
申请日：1993-06-22
申请人： FUJITSU LTD
发明人： TAKIZAWA YUJI , KAWAI MASAAKI , NAITO HIDETOSHI , TAJIMA KAZUYUKI , IKEDA TOSHIMI , KIMURA TERUO
IPC分类号： H03K5/00 , H03K17/00
摘要： PURPOSE:To eliminate a short periodic clock and to eliminate the malfunctions of various kinds of equipments operating by the clock by outputting the clock in a mask state which is held in an H level state over the period which is longer than a clock half period from a selector at the time of the switching operation of the selector. CONSTITUTION:When a mask command signal MSK becomes an H level, the input data of a data input terminal D or a mask command signal MASK is made to be outputted, and the mask control signals M1 and M2 from data and an output terminal Q are made to rise and are made an H level state by the rise timing of the first clocks CLK 1 and CLK 2 after the mask command signal MASK becomes the H level state by D flip flops 17A and 17B, in a control circuit 15. Thus, OR gates 10A and 10B are made a mask operation states and the clock outputs CLK 1M and CLK 2M from these are held in the H level. Namely, the switching completion signal EXCHG of an AND gate 18 is made to rise and a control signal S is made to be outputted from a D flip flop 16 to a selector 3.

89. 发明专利

JPH0572131B2 失效
公开(公告)号：JPH0572131B2
公开(公告)日：1993-10-08
申请号：JP23366587
申请日：1987-09-19
申请人： FUJITSU LTD
发明人： KAWAI MASAAKI , WATABE HISAKO
IPC分类号： H03H7/20 , H03H11/20

90. 发明专利

JPH05167151A LIGHT EMITTING ELEMENT DRIVING CIRCUIT 失效
公开(公告)号：JPH05167151A
公开(公告)日：1993-07-02
申请号：JP33082391
申请日：1991-12-13
申请人： FUJITSU LTD
发明人： IKEDA TOSHIMI , KAWAI MASAAKI , NAITO HIDETOSHI , TAKIZAWA YUJI , TAJIMA KAZUYUKI
IPC分类号： H01S5/042
摘要： PURPOSE:To provide a light emitting element driving circuit which can finely control an optical output. CONSTITUTION:A light emitting element driving circuit for controlling an optical output of a light emitting element comprises a converter 1 for converting a control signal Sc of an optical output into a control signal Sc' having a micro amplitude, and a current source circuit 2 for forming a driving current Id of the element according to the signal Sc', and finely controls the optical output of the element by the signal Sc of the output. Here, the converter 1 is formed of a linear circuit. Further, the converter 1 is formed of a nonlinear circuit in which the output of the circuit 2 made of a nonlinear element is made linear.

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