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1. 发明专利

JP2001313654A ATM DEVICE, ATM COMMUNICATION SYSTEM AND METHOD FOR SWITCHING VIRTUAL PATHS 失效
公开(公告)号：JP2001313654A
公开(公告)日：2001-11-09
申请号：JP2000132183
申请日：2000-05-01
申请人： FUJITSU LTD
发明人： EDAMURA YUICHIRO , YOKOYAMA MASAMI , YOSHIDA NORIHIRO , NAKADE HIROSHI , KONDO RYUICHI , KIUCHI KANEYA
IPC分类号： H04L12/28
摘要： PROBLEM TO BE SOLVED: To make it possible to fast switch to a standby virtual path without increasing a processing burden in the case a failure occurs in an active virtual path about an ATM device for transmitting and receiving an ATM cell, an ATM communication system and a virtual path switching method. SOLUTION: In the ATM device, the ATM communication system constructed by connecting a plurality of ATM devices and the virtual path switching method for switching the active virtual path to the standby virtual path, the ATM device includes interface parts 1-1 to 1-N, a switch part (SW) 2 and a supervisory control part 3, the respective interface parts are provided with pair tables 4-1 to 4-N where the standby virtual path is respectively set up for the active virtual path of their own interface part, routing tables 5-1 to 5-N where routing information is set up, a detecting means for an alarm cell, a generating and transmitting means for an automatic path switch cell, etc., and the interface parts autonomously switch the active virtual path where a failure occurs to the standby virtual path.

2. 发明专利

JPH09261236A NO-HIT EXTENSION SYSTEM FOR CROSS CONNECT DEVICE 失效
公开(公告)号：JPH09261236A
公开(公告)日：1997-10-03
申请号：JP6588896
申请日：1996-03-22
申请人： FUJITSU LTD
发明人： SUGANO KEIICHI , KONDO RYUICHI , SAKURAI HIROYA , FUJIMOTO TOSHIBUMI
IPC分类号： H04L12/931 , H04L12/943 , H04Q11/04 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To extent a switch function part without causing any hit of data by providing a filter which decides an exit path by means of the switch function part of a basic unit and prevents an input to the extension unit of cell-converted input data. SOLUTION: The switch function part 3 with the 8×8 cross connect function of the basic unit 1 decides the exit path based on virtual pass information of cell-converted input data and outputs cell-converted data. The switch function part 400 of the 64×64 cross connect function of the extension unit 2 inputs cell-converted data and cell-converted data from another basic unit, decides the exit path based on these kinds of virtual pass information and outputs cell-converted inputdata. Moreover, filters 80-87 and 900-955 prevents the input of cell-converted data to the extension unit 2, whose exit path is decided by the switch function part of the basic unit 1.

3. 发明专利

JP2530368B2 失效
公开(公告)号：JP2530368B2
公开(公告)日：1996-09-04
申请号：JP9704089
申请日：1989-04-17
申请人： FUJITSU LTD
发明人： NAITO HIDETOSHI , OOTSUKA TOMOYUKI , KAWAI MASAAKI , KONDO RYUICHI
IPC分类号： H01L33/00

4. 发明专利

JP2516349B2 失效
公开(公告)号：JP2516349B2
公开(公告)日：1996-07-24
申请号：JP104387
申请日：1987-01-08
申请人： FUJITSU LTD
发明人： KONDO RYUICHI
IPC分类号： H04B10/00 , H04B10/524 , H04B10/54 , H04B10/80 , H04B10/24 , H04B10/02

5. 发明专利

JPH06164623A BUFFER READING CONTROL SYSTEM 失效
公开(公告)号：JPH06164623A
公开(公告)日：1994-06-10
申请号：JP30709692
申请日：1992-11-17
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： YAMASHITA HARUO , KONDO RYUICHI , KOYANAGI TOSHINORI , SATO HIROYUKI , OBARA HITOSHI , UEDA HIROMI
IPC分类号： H04L1/22 , H04L12/48
摘要： PURPOSE:To temporarily store the cell trains in a buffer and to ensure the optimum control of a phase in a reading mode in regard of a buffer reading control system which stores the signal systems consisting of cell trains in a buffer and then reads out these signal systems. CONSTITUTION:The inputs 2 and 3 consisting of the cell trains are temporarily stored in the buffers 4 and 5 and then read out by a reading control circuit 1. Then a prescribed delayed variable is given to a reading cell timing pulse FP in response to the phase difference between the pulse FP and the head position detected by a cell head detecting part 11. Thus the reading control is applied to both buffers 4 and 5 by the pulse FP containing a prescribed delayed variable.

6. 发明专利

JPH0626326B2 失效
公开(公告)号：JPH0626326B2
公开(公告)日：1994-04-06
申请号：JP23891685
申请日：1985-10-25
申请人： FUJITSU LTD
发明人： IGUCHI KAZUO , OOTSUKA TOMOYUKI , KYONAGA TETSUYA , KONDO RYUICHI
IPC分类号： H04B10/556 , H04B10/00 , H04L25/02

7. 发明专利

JPH05145430A DATA SPEED CONVERSION CIRCUIT 失效
公开(公告)号：JPH05145430A
公开(公告)日：1993-06-11
申请号：JP30632391
申请日：1991-11-21
申请人： FUJITSU LTD
发明人： WAKIZAKA TAKAAKI , YAMASHITA HARUO , ISHIHARA TOMOHIRO , KONDO RYUICHI , SUDO TOSHIYUKI
IPC分类号： G06F5/00 , H03M9/00 , H04L13/10
摘要： PURPOSE:To decrease the gate occupancy rate and the rate of the mount area of a bit string detection section by providing the bit string detection section not to a high speed side but to a low speed side. CONSTITUTION:The circuit is provided with a bit string detection section 110 detecting a specific bit string from low speed data based on a low speed clock generated from a high speed clock by a 1/n frequency division counter 1, a control signal generating section 120 generating a control signal corresponding to the result of the detection by the bit string detection section 110 and a control circuit 130 varying a phase of the counter 1 by giving a reset signal to deviate a specific bit of the low speed clock from the counter 1 at a bit location designated by the control signal, and the control circuit 130 distributes the pulse from the counter 1 to pulses shifted by one bit each and gives them to two delay control sections respectively and gives a control signal generated for the purpose of giving a delay of a specific bit to the delay control sections, from which a reset signal is generated to change the phase of the counter 1.

8. 发明专利

JPH04337935A DATA SWITCHING SYSTEM 失效
公开(公告)号：JPH04337935A
公开(公告)日：1992-11-25
申请号：JP13956191
申请日：1991-05-15
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ISHIHARA TOMOHIRO , YAMASHITA HARUO , KONDO RYUICHI , WAKIZAKA TAKAAKI , SUDO TOSHIYUKI
IPC分类号： H04L1/22
摘要： PURPOSE:To execute switching without fail between data cells of active and auxiliary systems by inserting a switching flag cell into the data cell. CONSTITUTION:The same data cells always flow to the active and auxiliary system and the data cell of the active system is selected and outputted normally. Cell insertion parts 1 and 2 for active system and auxiliary system are provided to insert the switching flag cells to the respective data cells of the active and auxiliary systems, and a switching part 3 is provided to input the data cells outputted from the cell insertion parts 1 and 2, to switch the system to the auxiliary system and to output the data cell after the switching flag cell of the auxiliary system when the switching flag cell in the data cell of the active system is detected. When the switching flag cell in the data cell of the auxiliary system is detected, the system is switched back to the active system. Namely, since the data cell is selectively outputted with the switching flag as the border, switching is enabled without being interrupted, and wrong switching can be prevented.

9. 发明专利

JPH02228836A OPTICAL COMMUNICATION SYSTEM 失效
公开(公告)号：JPH02228836A
公开(公告)日：1990-09-11
申请号：JP5050989
申请日：1989-03-02
申请人： FUJITSU LTD
发明人： KONDO RYUICHI , OTSUKA TOMOYUKI
IPC分类号： G02F2/00 , H04J14/00 , H04J14/02
摘要： PURPOSE:To attain the matching of phases of a data of a different wavelength from even that of a high speed data with an optical receiver by using a guide path of refractive index variable type. CONSTITUTION:One of output clocks of optical reception sections 500-1-500-n is used as a reference clock, it is fed to one input terminal of phase comparators 950-1-950-(n-1), and a clock being an output of other (n-1) sets of the optical reception sections is fed to the other input, the phase of the both is compared and a voltage corresponding to the phase difference is outputted. The output voltage is fed respectively to the refractive index variable type waveguide paths 900-1-900-(n-1) to vary the phase of the optical signal data of the output and the phase of the clocks being the outputs of the (n-1) sets of the optical reception sections is matched with the phase of the reference clock. Thus, the phase of the data of the different wavelength even in the high speed data is matched with a circuit whose size is made small in the optical receiver.

10. 发明专利

JPH01213042A MULTIPLEXING SYSTEM 失效
公开(公告)号：JPH01213042A
公开(公告)日：1989-08-25
申请号：JP3928388
申请日：1988-02-22
申请人： FUJITSU LTD
发明人： YAMASHITA HARUO , OTSUKA TOMOYUKI , KONDO RYUICHI , KAWAI MASAAKI
IPC分类号： H04J3/00
摘要： PURPOSE:To simplify a high-speed signal processing circuit by multiplexing parallel scramble output and (k) bit data at every CH, multiplexing the signal of the whole CH after prescribed delay processing and enabling the processing of scramble or the like at a low-frequency stage to be executed. CONSTITUTION:The analogue signals Ai1-AiN are digitized by A/D conversion circuits 101-10N and scrambled in parallel by scrambles 111-11N. The PN signal of an M-system which is shifted only (n+k) at every clock by each scrambler and a value in a state that it is shifted only (n+k) bit for the adjacent scrambler is set to initial value setting circuits 121-12N. The parallel scramble output and the (k) bit data column are multiplexed at every channel(CH) by multiplexing circuits 131-13N. The channel is delayed so as to be delayed by (k) bit from the adjacent CH by a delay circuit 14 by inputting the multiplexing the output at every CH. The signal of the whole CH of the circuit 14 which are processed like that are multiplexed by a multiplexing circuit 15.

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