专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明专利

JPS5920032A Trap control circuit 失效
标题翻译：捕捉控制电路
公开(公告)号：JPS5920032A
公开(公告)日：1984-02-01
申请号：JP13017782
申请日：1982-07-26
申请人： Fujitsu Ltd
发明人： KUBOU KATSUMI , AOKI TAKASHI
IPC分类号： G06F9/22 , G06F9/48 , G06F13/12 , G06F13/24
CPC分类号： G06F9/4812
摘要： PURPOSE:To prevent a request from being accepted when the acceptance of the request is impossible, by using a mask bit of the preceding same instruction to discriminate whether or not the request can be accepted when an error exists in the micro instruction of a CPU. CONSTITUTION:CS (control storage) read data is set to an instruction register. Consequently, mask bits are set to an FF1; and if CS read data has no errors, a CS error bar signal CSERR is H-level, and a signal CSERR is L-level, and the mask bit set to the FF1 are sent through gates AG1 and OG and are used to discriminate whether or not the request can be accepted. Since the mask bit of an instruction A is 1, 1 is set to an FF2. When an instruction A' is next read, a check circuit detects that the instruction A' has an error, and the signal CSERR is set to 1. Consequently, the gate AG1 is closed, and a gate AG2 is opened, and contents of the FF2, namely, mask bit ''1'' of the preceding instruction A is outputted through the gate AG2 and OG.
摘要翻译：目的：为了防止在不可能接受请求时接受请求，通过使用前面相同指令的掩码位来判断在微指令中存在错误是否可以接受该请求。构成：CS（控制存储）读取数据设置为指令寄存器。因此，掩码位被设置为FF1; CS读数据没有错误时，CS误差信号CSERR为H电平，信号CSERR为L电平，通过门AG1，OG发送设置为FF1的掩码位，用于判别是否或者不可以接受请求。由于指令A的掩码位为1，所以设置为FF2。当下一次读取指令A'时，检查电路检测到指令A'具有错误，并且信号CSERR被设置为1.因此，门AG1闭合，并且门AG2被打开，并且内容通过门AG2和OG输出FF2，即前一指令A的掩码位“1”。

82. 发明专利

JPS57205881A TRAP CONTROLLING SYSTEM 失效
公开(公告)号：JPS57205881A
公开(公告)日：1982-12-17
申请号：JP8918581
申请日：1981-06-10
申请人： FUJITSU LTD
发明人： AOKI TAKASHI
IPC分类号： G06F12/08 , G06F13/12
摘要： PURPOSE:To effectively use the access time of the main memory and to improve the processing efficiency of the central processing device by restarting an instruction process in an idle time until the data from a main storage device is fetched. CONSTITUTION:When a transfer request DRQ is made from a channel CH, a trap cycle TRPC is turned on by an OR circuit 41, and a central processing device stops its instruction processig being performed until the request is made. in case where no data exist in a buffer memory when a memory fetch MSF is turned on, an HIT is turned on and a main memory is accessed. At this stage, a return cycle signal RTNFF from a subroutine of a microprogram is turned on and instruction processing is performed. The trap cycle TRPC is again turned on just one cycle before returning of the data from the main memory.

83. 发明专利

JPS57162038A ERROR CORRECTING CODE CHECK SYSTEM 失效
公开(公告)号：JPS57162038A
公开(公告)日：1982-10-05
申请号：JP4748381
申请日：1981-03-31
申请人： FUJITSU LTD
发明人： AOKI TAKASHI
IPC分类号： G06F11/10 , G06F9/22 , G06F11/08
摘要： PURPOSE:To make an exclusive bit for a checking code of a microprogram unnecessary, and to decrease the number of bits per 1 word, by utilizing a characteristic of a horizontal microprogram. CONSTITUTION:1 word of a horizontal microporgram is constituted of 31 bits consisting of 0-30, the bits 0-5 are set to the next address NA, and an address on a control storage device is designated by the following bits 6-30. A field of the bits 6-11 of this program is constituted of an ALUX for designating one input of an operating circuit ALU, an ALUY for designating the other input, the ALU for designating adition, subtraction, etc., and an ARI and an BRI for designating an input of a register AR and BR, respectively. Also, the bits 12-17 are used for designating a condition used for a conditional branch, etc., the bits 18- 23 are used as an input for designating an input of a shifter SH, and the bits 24-29 are used as an address IMM of an extension register. In this way, by utilizing a characteristic of the program, an exclusive bit for a checking code is made unnecessary, and the number of bits per 1 word is decreased.

84. 发明专利

JPS57162031A ADDRESS STACK CONTROL SYSTEM 失效
公开(公告)号：JPS57162031A
公开(公告)日：1982-10-05
申请号：JP4827781
申请日：1981-03-31
申请人： FUJITSU LTD
发明人： SAKAI KENJI , AOKI TAKASHI , NAKAO SADAO
IPC分类号： G06F9/22 , G06F9/26 , G06F9/42
摘要： PURPOSE:To lighten the burden of a program generating person, and to easily change a return instruction or a routine of the return instruction, by automatically storing the control information in a stack, and making it unnecessary that the generating person gives the return instruction over again. CONSTITUTION:A data for generating an address data of a main routine and subroutines 2, 3 stored in a microprogram storage device (CS) 6 from a computer is supplied to a CS red address generating circuit 5. In this circuit 5, an address of the CS 6 is generated, and a stack point being a write and read-out address is stored in a stack 4. Also, the address control information is provided to the stack 4 and the circuit 5, and an address of the control information generated by the circuit 5 is stored in address control information storage areas 7-0-7-n. In this state, the routine 1 is executed, and after that, when the control is shifted to the subroutines 2, 3, a return address to the routines 2, 3 and the address control information informing that the control is shifted after the return instruction has been issued are stored in the stack 4.

85. 发明专利

JPS57113496A BANK CONTROL SYSTEM OF CONTROL STORAGE 失效
公开(公告)号：JPS57113496A
公开(公告)日：1982-07-14
申请号：JP18907680
申请日：1980-12-29
申请人： FUJITSU LTD
发明人： SAKAI KENJI , AOKI TAKASHI
IPC分类号： G06F12/16 , G06F11/16 , G11C29/00
摘要： PURPOSE:To detach a bank in which a fualt has occurred, and to continuously operate other banks, by controlling each divided control storage bank through a bank address register, a comparator, etc. of each bank. CONSTITUTION:The high rank part of an access address forming a bank access address from an address register 1 is compared with a bank address stored in bank address registers 31- provided on each divided control storage bank 21-, by comparators 41-. Subsequently, in case of coincidence, gates 61- are controlled by a flag sigal of a high level, which passes through AND gates 51-, and banks 21- are selected in accordance with access. Accordingly, when the high rank part of the address corresponding to the banks 21- in which a fault has occurred is detached, the bank in which the fault has occurred is detached, and other banks are operated continuously as they are.

86. 发明专利

JPS56111197A TWOOBIT ERROR CORRECTION SYSTEM 失效
公开(公告)号：JPS56111197A
公开(公告)日：1981-09-02
申请号：JP1132880
申请日：1980-02-01
申请人： FUJITSU LTD
发明人： AOKI TAKASHI
IPC分类号： G06F11/10 , G06F12/16 , H03M13/29
摘要： PURPOSE:To enable to correct 2-bit errors without using the two-bit error correcting code (ECC), by the parity check per each block of a plurality of data added with the 2-bit error detection code for error correction. CONSTITUTION:A plurality of data added with ECC having 1-bit error correction 2-bit error detecting functions in which one word has a given bit, are stored in the memory 1. At the same time, parity bits are provided every bit location of each word and this is stored in the block parity area 1-2 of the memory 1. With this state, the data such as address YA of the memory 1 are read out and a bit error is detected with ECC of the error correcting code area, then checking is made with the parity data of the area 1-2 for each data block per bit, and the error production bits dm, dn are detected from the error presence bits Xm, Xn for the address YA, allowing to correct the 2-bit error with a simple constitution not requiring 2-bit the correction ECC.

87. 发明专利

JPS5629759A BYTE MARK REGISTER CONTROL SYSTEM FOR MEMORY DEVICE 失效
公开(公告)号：JPS5629759A
公开(公告)日：1981-03-25
申请号：JP10461479
申请日：1979-08-17
申请人： FUJITSU LTD
发明人： AOKI TAKASHI , SATOU KIYOSUMI , MIYAJIMA SHIGERU , SAGARA HISAJIROU , FURUTA SHIGEKI
IPC分类号： G06F12/04 , G06F13/00
摘要： PURPOSE:To eliminate both the production and transfer of the byte mark prior to the transfer of the writing data by setting the fixed byte mark pattern to the byte mark register after completion of the instruction fetching, thus ensuring a high-speed memory access. CONSTITUTION:It is supposed that the instruction fetching completes with the signal IEND turned to 1. And thus ''1111'' of the fixed byte mark generating circuit 8 is delivered from the OR circuit 10. And if the signals SBMU, SMBFL and SMBL are off and the signal ADR29 is ''1'' each, the pattern ''1111'' is set to the byte mark register 7-1. And in case the signal ADR29 is ''1'', the pattern ''1111'' is set also to the register 7-0. In such way, the fixed byte mark pattern ''1111'' is set to the registers 7-0 and 7-1 each after completion of the instruction fetching. Thus the production and transfer of the byte mark prior to the transfer of the writing data can be eliminated. As a result, the memory access is possible in a high speed.

88. 发明专利

JPS5629743A LOCAL MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS5629743A
公开(公告)日：1981-03-25
申请号：JP10461379
申请日：1979-08-17
申请人： FUJITSU LTD
发明人： AOKI TAKASHI , SATOU KIYOSUMI , MIYAJIMA SHIGERU , ITOU SHIYOUHEI , FURUTA SHIGEKI
IPC分类号： G06F7/00 , G06F7/76 , G06F9/34
摘要： PURPOSE:To realize a high-speed acceleration by writing both the higher- and lower-rank m-bit data of the 2m-bit data into the designated addresses of the different local memory units during the counting of the floating points. CONSTITUTION:In the local memory device containing the local memory units 7-0 and 7-1 having the m-bit data width each, the local memory registers 2-0 and 2-1 designate the base register and the index register each to carry out the reading in the case of the address calculation. When the data is written, the same contents are secured between registers 2-0 and 2-1. And the same data is written into the same address of the units 7-0 and 7-1. In the case of the floating point arithmetic, both the higher- and lower-rank m bits of the result obtained through the operation carried out at the high-speed arithmetic part 1 are sent to local memory writing registers 5-0 and 5-1 each to be stored in the designated floating point registers of units 7-0 and 7-1 each. In this case, registers 2-0 and 2-1 have the same address information. As a result, not only the address calculation but the floating point arithmetic can be performed in a high speed.

89. 发明专利

JPS5622293A CONTROL SYSTEM FOR REPLACEMENT MEMORY 失效
公开(公告)号：JPS5622293A
公开(公告)日：1981-03-02
申请号：JP9711079
申请日：1979-07-30
申请人： FUJITSU LTD
发明人： TANIGUCHI SHIYOUZOU , TAKAMURA MORIYUKI , AOKI TAKASHI , FURUTA SHIGEKI
IPC分类号： G06F12/16 , G11C29/00
摘要： PURPOSE:To enable to obtain the memory unit of high reliability without increasing the memory capacity of replacement, by judging whether it is correctable error or not when an error is taken place, and switching the memory to the replacement memory to the replcement memory if impossible for correction. CONSTITUTION:When the write-in data from external unit is given to the memory unit B, output l is outputted from the write-in data selection circuit WS, and it is fed to the memory M, check bit generation circuit CG, and replacememt memory write-in data selection circuit MPX. If no replacement memory MC is used, the readout data l4, l5, of M are fed to the readout data correction circuit DC as the data l6 at the readout data selection circuit RS and also fed to the syndrome calculation circuit SG. If an error is detected in SG, the signal l7 is given to the decoder 1 and data are corrected at DC. This signal l7 is also given to the syndrome memory. If the both are in agreement, either one of MD or MC of the memory section M is switched to the replacement memory MA.

90. 发明专利

JPH11288398A NETWORK CONTROL METHOD, MEDIUM AND NETWORK CONTROL SYSTEM 失效
公开(公告)号：JPH11288398A
公开(公告)日：1999-10-19
申请号：JP9164398
申请日：1998-04-03
申请人： FUJITSU LTD
发明人： HAMANAKA MAKOTO , AOKI TAKASHI
IPC分类号： G06F13/10 , G06F9/06 , G06F13/14
摘要： PROBLEM TO BE SOLVED: To provide a network control method and a medium capable of executing setting for each category on a controller side, setting control for handling only a specified category or the control for uniformly handling the specified category on the controller side and automatically installing only the control information of a device belonging to the category to be handled to a controller. SOLUTION: In this network control method, the device 20 is provided with category data 20b relating to the present device 20 and the setting relating to the connection of the present device 20, the controller 10 is provided with the setting relating to the connection of the device 20 for each category of the device 20 and the controller 10 decides whether or not to obtain the device driver and control information of the device 20 corresponding to the combination of the setting on the side of the device 20 and the setting on the side of the controller 10.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式