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    • 77. 发明专利
    • Flip-flop circuit and frequency divider circuit
    • FLIP-FLOP电路和频率分路电路
    • JP2011135297A
    • 2011-07-07
    • JP2009292629
    • 2009-12-24
    • Panasonic Corpパナソニック株式会社
    • YAMAGUCHI SATOSHI
    • H03K3/3562H03K3/037H03K23/50H03K23/66
    • H03K3/356139H03K3/012H03K3/35625H03K23/662
    • PROBLEM TO BE SOLVED: To improve the maximum operating frequency by reducing power consumption in a flip-flop circuit. SOLUTION: A first data holding circuit (18) of a master-side element (100) and a second data holding circuit (19) of a slave-side element (200), are constituent elements of a flip-flop circuit. The flip-flop circuit has a function for switching the ON/OFF operating state of operations of the first/second data holding circuits. The flip-flop circuit makes timing control to each of the first/second data holding circuits so as to reduce an unnecessary current, to eliminate effects of a parasitic capacitance, to operate at a low power consumption, and to have the high maximum operating frequency. COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:通过降低触发器电路的功耗来提高最大工作频率。 解决方案:从属侧元件(200)的主器件元件(100)和第二数据保持电路(19)的第一数据保持电路(18)是触发器电路的组成元件 。 触发器电路具有用于切换第一/第二数据保持电路的操作的ON / OFF操作状态的功能。 触发器电路对第一/第二数据保持电路中的每一个进行定时控制,以减少不必要的电流,消除寄生电容的影响,以低功耗工作,并具有高的最大工作频率 。 版权所有(C)2011,JPO&INPIT
    • 78. 发明专利
    • Comparator and analog-to-digital converter
    • 比较器和模拟数字转换器
    • JP2010109937A
    • 2010-05-13
    • JP2008282387
    • 2008-10-31
    • Tokyo Institute Of Technology国立大学法人東京工業大学
    • MATSUZAWA AKIRAMIYAHARA MASAYA
    • H03K5/08H03M1/36
    • H03K5/2481H03K3/356139H03K5/249H03M1/0682H03M1/204H03M1/365
    • PROBLEM TO BE SOLVED: To solve the problem of timing deviation between two clock signals of different polarities existing in the conventional comparator, and to enable low-power operation, in a comparator and an A/D (analog-to-digital) converter provided with the same. SOLUTION: The comparator is provided, which is provided with: a differential amplifier circuit to which first and second input voltage signals and a clock signal are inputted, and which operates according to the clock signal and outputs first and second output voltage signals corresponding to values of the first and second input voltage signals, respectively, and amplified; and a differential latch circuit which operates according to the first and second output voltage signals, holds and outputs the comparison result of the first and second input voltage signals. The A/D converter is also provided, which is provided with a plurality of comparators. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:为了解决现有比较器中存在的不同极性的两个时钟信号之间的定时偏差的问题并且能够实现低功率操作,在比较器和A / D(模数转换器 )转换器。 解决方案:提供比较器,其具有:差分放大器电路,第一和第二输入电压信号和时钟信号输入到该差分放大器电路,并且根据时钟信号进行操作,并输出第一和第二输出电压信号 分别对应于第一和第二输入电压信号的值并被放大; 以及根据第一和第二输出电压信号工作的差分锁存电路,保持并输出第一和第二输入电压信号的比较结果。 还提供了A / D转换器,其设置有多个比较器。 版权所有(C)2010,JPO&INPIT