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71. 发明专利

JP2007096241A Semiconductor device and method of manufacturing same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007096241A
公开(公告)日：2007-04-12
申请号：JP2005297955
申请日：2005-10-12
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KITADA HIDEKI , OTSUKA NOBUYUKI , SHIMIZU NORIYOSHI , NAKAO YOSHIYUKI
IPC分类号： H01L21/3205 , H01L23/52
CPC分类号： H01L23/53238 , H01L21/76831 , H01L21/76846 , H01L21/76855 , H01L21/76864 , H01L21/76867 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for sufficiently securing adhesion properties of a wiring member and prevent it from being peeled off during the time period until a barrier layer is formed that has a function of enhancing adhesion properties. SOLUTION: (a) An interlayer dielectric provided with a recess is formed on a semiconductor substrate. (b) An adhesion layer is formed on the inner surface of the recess and top surface of the interlayer dielectric. (c) The surface of the adhesion layer is covered with an auxiliary film made of a Cu alloy containing a first metal element. (d) A conductive member containing a second metal element other than the first metal element is filled in the recess, and is also deposited on the auxiliary film. (e) Heat treatment is performed to make atoms of the first metal element in the auxiliary film segregate on the inner surface of the recess. The adhesion layer contains more elements for enhancing the adhesion of the auxiliary film than when the auxiliary film is deposited directly on the surface of the interlayer dielectric. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，用于充分确保布线构件的粘合性能并且防止其在形成具有增强粘合力的功能的阻挡层之前的时间段内被剥离属性。解决方案：（a）在半导体衬底上形成设置有凹部的层间电介质。（b）在凹陷的内表面和层间电介质的顶表面上形成粘附层。（c）粘附层的表面覆盖有由含有第一金属元素的Cu合金制成的辅助膜。（d）含有除了第一金属元件之外的第二金属元件的导电元件填充在凹部中，并且也沉积在辅助膜上。（e）进行热处理，使辅助膜中的第一金属元素的原子在凹部的内表面分离。当粘附层直接沉积在层间电介质的表面上时，粘合层含有更多的用于增强辅助膜粘附的元件。版权所有（C）2007，JPO＆INPIT

72. 发明专利

JP2007067107A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007067107A
公开(公告)日：2007-03-15
申请号：JP2005250046
申请日：2005-08-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIMIZU NORIYOSHI , OTSUKA NOBUYUKI , KITADA HIDEKI , NAKAO YOSHIYUKI
IPC分类号： H01L21/3205 , C23C16/18 , H01L21/28 , H01L21/285 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/76831 , H01L21/76844 , H01L21/76855 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can ensure sufficient adhesive properties of a wiring member, and can prevent a separation of the wiring member for a period during which a barrier layer having a function of increasing adhesive properties together is formed. SOLUTION: A recess is formed in an insulating film formed on a semiconductor substrate (a1). A first film made of Mn is formed so as to cover an inner face of the recess and an upper face of the insulating film by a CVD method (a2). A conductive material having Cu as a main component is deposited on the first film, and also, the conductive material is charged into the recess (a3). The semiconductor substrate is annealed (a4). COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以确保配线构件的充分粘合性能的半导体装置的制造方法，并且能够防止配线构件在具有增加功能的阻挡层的期间分离一起形成粘合性。解决方案：在形成在半导体衬底（a1）上的绝缘膜中形成凹部。通过CVD方法（a2）形成由Mn构成的第一膜，以覆盖凹部的内表面和绝缘膜的上表面。将具有Cu作为主要成分的导电材料沉积在第一膜上，并且还将导电材料装入凹部（a3）中。半导体衬底退火（a4）。版权所有（C）2007，JPO＆INPIT

73. 发明专利

JP3803631B2 Semiconductor device and a method of manufacturing the same 有权
公开(公告)号：JP3803631B2
公开(公告)日：2006-08-02
申请号：JP2002323493
申请日：2002-11-07
申请人：株式会社東芝
发明人：一明中嶋 , 恭一須黒
IPC分类号： H01L21/28 , H01L21/8238 , H01L21/285 , H01L21/768 , H01L27/092
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76855 , H01L21/823814 , H01L21/823871 , H01L27/092

74. 发明专利

JP2006156614A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006156614A
公开(公告)日：2006-06-15
申请号：JP2004343443
申请日：2004-11-29
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： FURUYA AKIRA , OTSUKA NOBUYUKI , OKAMURA HIROSHI , OGAWA SHINICHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/336 , H01L29/78
CPC分类号： H01L21/76846 , H01L21/318 , H01L21/3185 , H01L21/76855 , H01L21/76862 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is provided with a barrier metal having high adhesiveness and diffusion preventive property, and also to provide its manufacturing method. SOLUTION: The method for manufacturing a semiconductor device includes steps of: forming a first layer made of a material containing silicon on a substrate; forming a second layer containing metal and nitrogen on the first layer; and exposing the second layer to active species that is obtained from atmospheric plasma containing a reducing gas. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有高粘合性和扩散防止性的阻挡金属的半导体器件，并且还提供其制造方法。解决方案：半导体器件的制造方法包括以下步骤：在基板上形成由含有硅的材料制成的第一层; 在所述第一层上形成含有金属和氮的第二层; 并将第二层暴露于由含有还原气体的大气等离子体获得的活性物质。版权所有（C）2006，JPO＆NCIPI

75. 发明专利

JP2005354029A Semiconductor device with low contact resistance and its manufacturing method 审中-公开
标题翻译：具有低接触电阻的半导体器件及其制造方法
公开(公告)号：JP2005354029A
公开(公告)日：2005-12-22
申请号：JP2004382103
申请日：2004-12-28
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
发明人： AHN TAE-HANG
IPC分类号： H01L21/28 , H01L21/205 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/48 , H01L23/485 , H01L23/52 , H01L23/522 , H01L27/108 , H01L29/41 , H01L29/80 , H01L29/94
CPC分类号： H01L21/28525 , H01L21/0243 , H01L21/02532 , H01L21/02576 , H01L21/02592 , H01L21/0262 , H01L21/76802 , H01L21/76814 , H01L21/76843 , H01L21/76847 , H01L21/76855 , H01L21/76877 , H01L21/76889 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with contact resistance which satisfies electrical characteristics with an ultrahigh integrated device, and to provide its manufacturing method. SOLUTION: The semiconductor device includes a semiconductor substrate structure with a contact hole formed so that a predetermined portion of a semiconductor substrate may be exposed, and a contact plug, wherein the contact plug is constituted by an epitaxial silicon layer which is formed in the contact hole and buries a portion of an inside of the contact hole, and metal layers which are formed on the epitaxial silicon layer and bury its remainder of the inside of the contact hole. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有与超高集成器件满足电特性的接触电阻的半导体器件，并提供其制造方法。解决方案：半导体器件包括半导体衬底结构，其具有形成为可以暴露半导体衬底的预定部分的接触孔以及接触插塞，其中接触插塞由形成的外延硅层构成在接触孔中并埋入接触孔的内部的一部分，以及形成在外延硅层上的金属层，并埋入其接触孔的内部的其余部分。版权所有（C）2006，JPO＆NCIPI

76. 发明专利

JP2005277390A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005277390A
公开(公告)日：2005-10-06
申请号：JP2005027756
申请日：2005-02-03
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： KOIKE JUNICHI , WADA MAKOTO , SHIBATA HIDEKI , SHIMIZU NORIYOSHI , TAKAHASHI SHINGO , NISHIKAWA SATORU , YOSHIMARU MASAKI , USUI TAKAKIMI , NASU ISATO
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/532
CPC分类号： H01L21/76844 , H01L21/76831 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76867 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which contributes to a reliability improvement and a resistance reduction of a wiring structure. SOLUTION: A layer dielectric 41 including an aperture 42 is disposed on a semiconductor substrate. A wiring body layer 46 with Cu as a main component is buried in the aperture 42. A barrier film 44 is interposed between the layer dielectric 41 and the wiring body layer 46 inside the aperture 42. The barrier film 44 is mainly composed of a chemical compound of a predetermined metallic element and a constitutive element of the layer dielectric 41. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供有助于可靠性提高和布线结构的电阻降低的半导体器件。解决方案：包括孔42的层介质41设置在半导体衬底上。具有Cu作为主要成分的布线体层46被掩埋在孔42中。阻挡膜44介于孔42内部的层介质41和布线体层46之间。阻挡膜44主要由化学预定金属元素的化合物和电介质层41的组成元素。版权所有：（C）2006，JPO＆NCIPI

77. 发明专利

JP3648480B2 Semiconductor device and a method of manufacturing the same 有权
公开(公告)号：JP3648480B2
公开(公告)日：2005-05-18
申请号：JP2001395237
申请日：2001-12-26
申请人：株式会社東芝
发明人：祥代伊藤 , 孝川ノ上 , 正彦蓮沼
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/76801 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76855 , H01L21/76888 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00

78. 发明专利

JP2005504885A Barrier formation using a novel sputter deposition method 审中-公开
公开(公告)号：JP2005504885A
公开(公告)日：2005-02-17
申请号：JP2003533324
申请日：2002-07-25
申请人：アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人：ハフィツ，ファロークアハマド， , ホー，スンウィー， , ヨンワー，クリスチャ， , サン，ホーユー， , キ，ワンユーン，
IPC分类号： C23C14/58 , C23C14/06 , C23C16/06 , C23C16/24 , H01L21/285 , H01L21/768
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/2855 , H01L21/28556 , H01L21/28562 , H01L21/76843 , H01L21/76855 , H01L21/76864
摘要：金属又は金属ケイ化物のバリア層を形成する方法及び装置が提供される。１つの態様において、シリコン材料が配置された基板を基板処理システムに配置するステップと、第１処理チャンバにおいて上記基板の表面に第１金属層を堆積するステップと、シリコン材料及び第１金属層を反応させることにより金属ケイ化物層を形成するステップと、第２処理チャンバにおいて上記基板にその場で第２金属層を堆積するステップとを備えた基板処理方法が提供される。別の態様において、上記方法は、ロードロックチャンバと、第１基板移送チャンバ及び第２基板移送チャンバを含む中間基板移送領域と、上記第１基板移送チャンバに結合された物理的気相堆積処理チャンバと、上記第２基板移送チャンバに結合された化学的気相堆積処理チャンバとを備えた装置において実行される。
【選択図】図１

79. 发明专利

JP3528665B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP3528665B2
公开(公告)日：2004-05-17
申请号：JP6443099
申请日：1999-03-11
申请人：セイコーエプソン株式会社
发明人：直弘守屋 , 通雄朝比奈 , 和己松本 , 英司鈴木
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L23/485 , H01L23/532
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/76801 , H01L21/76819 , H01L21/76843 , H01L21/76855 , H01L21/76856 , H01L21/76864 , H01L21/76868 , H01L21/76886 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00

80. 发明专利

JP2003318395A Manufacturing method for semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2003318395A
公开(公告)日：2003-11-07
申请号：JP2002118163
申请日：2002-04-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： FUJII YUJI
IPC分类号： H01L21/28 , H01L21/336 , H01L21/74 , H01L21/768 , H01L29/417 , H01L29/739 , H01L29/78
CPC分类号： H01L21/76846 , H01L21/743 , H01L21/76843 , H01L21/76855 , H01L21/76882 , Y10T428/12542
摘要： PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device having a power transistor. SOLUTION: After a conductor film 15a of titanium tungsten is deposited on the principal surface of a semiconductor substrate 1 in which grooves 11 and 13 are formed, a conductor film 16a of aluminum is deposited. Consecutively, the conductor film 16a is reflowed and poured into the grooves 11 and 13. Then, by depositing conductor films 16b and 16c while heating, the conductor films 16a, 16b and 16c are poured into the grooves 11 and 13. By providing the conductor film 15a, the reaction of the aluminum in the conductor films 16a-16c to the silicon of the semiconductor substrate 1 is restrained or prevented at the reflowing of the conductor films 16a-16c. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提高具有功率晶体管的半导体器件的可靠性。解决方案：在形成有沟槽11和13的半导体衬底1的主表面上沉积钛钨的导体膜15a之后，淀积铝的导体膜16a。导体膜16a连续地回流并倒入槽11和13中。然后，通过在加热时沉积导体膜16b和16c，将导体膜16a，16b和16c注入槽11和13中。通过提供导体在导体膜16a-16c的回流下，抑制或防止导体膜16a-16c中的铝与半导体衬底1的硅的反应。版权所有（C）2004，JPO

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