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71. 发明专利

JPS617754B2 JPS617754B2 - 失效
公开(公告)号：JPS617754B2
公开(公告)日：1986-03-08
申请号：JP11952179
申请日：1979-09-17
申请人： Mitsubishi Electric Corp
发明人： TSUBOCHI NATSUO , DENDA MASAHIKO , HIRATA KATSUHIRO , KINOSHITA SHIGEJI , HARADA HIROTSUGU , ABE HARUHIKO
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10805

72. 发明专利

JPS5927212B2 JPS5927212B2 - 失效
公开(公告)号：JPS5927212B2
公开(公告)日：1984-07-04
申请号：JP12337179
申请日：1979-09-25
申请人： Mitsubishi Electric Corp
发明人： ABE HARUHIKO , DENDA MASAHIKO , HIRATA KATSUHIRO , KINOSHITA SHIGEJI , TSUBOCHI NATSUO , HARADA HIROTSUGU
IPC分类号： B01J19/08 , C23F4/00 , H01L21/30 , H01L21/302 , H01L21/3065 , H05H1/46

73. 发明专利

JPS5913592B2 JPS5913592B2 - 失效
公开(公告)号：JPS5913592B2
公开(公告)日：1984-03-30
申请号：JP7989579
申请日：1979-06-22
申请人： Mitsubishi Electric Corp
发明人： ABE HARUHIKO , HARADA HIROTSUGU , TSUBOCHI NATSUO , YONEDA MASAHIRO , OOHAYASHI YOSHIKAZU
IPC分类号： C23F4/00 , C23F1/00 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L27/00

74. 发明专利

JPS592377B2 JPS592377B2 - 失效
公开(公告)号：JPS592377B2
公开(公告)日：1984-01-18
申请号：JP9291278
申请日：1978-07-28
申请人： Mitsubishi Electric Corp
发明人： ABE HARUHIKO , TSUBOCHI NATSUO , NISHIMOTO AKIRA , MYAKE KUNIAKI
IPC分类号： H01L29/78 , H01L21/31 , H01L21/316 , H01L21/768

75. 发明专利

JPS57160155A MULTI-LAYER SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS57160155A
公开(公告)日：1982-10-02
申请号：JP4687581
申请日：1981-03-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： ABE HARUHIKO , ITAKURA HIDEAKI , HIRATA KATSUHIRO , YONEDA MASAHIRO , NISHIOKA KIYUUSAKU
IPC分类号： H01L27/00 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L25/065
摘要： PURPOSE:To easily form connecting wires connecting integrated circuits by a method wherein connecting impurity diffusion layers are formed at the first and the second inclined edge faces in each semiconductor integrated circuit and the diffusion layers are connected by connecting wiring metals. CONSTITUTION:Semiconductor integrated circuits 12, 13, 14 are respectively isolated by inserting insulating films 15, 16 between each semiconductor integrated circuit and are stacked. The stacked left and right faces are formed to provide slopes with a predetermined angle by using each kind of chemical or gas plasma. Connecting impurity diffusion layers 12a, 12b, 13a, 13b, 14a, 14b with predetermined depth are formed at the inclined edge faces of the circuits 12, 13, 14 by a thermal diffusion method or an ion implantation method. The diffusion layers 12a and 13a are connected by the first connecting wiring metal layer 17 and the diffusion layers 13b and 14b are connected by the second connecting wiring metal layer 18. And a surface protective film 19 is formed around the multi-layer semiconductor integrated circuits.

76. 发明专利

JPS57132329A FINE PROCESSING METHOD 失效
公开(公告)号：JPS57132329A
公开(公告)日：1982-08-16
申请号：JP1860681
申请日：1981-02-10
申请人： MITSUBISHI ELECTRIC CORP
发明人： NISHIOKA KIYUUSAKU , ITAKURA HIDEAKI , HIRATA KATSUHIRO , ABE HARUHIKO , YONEDA MASAHIRO
IPC分类号： H01L21/302 , H01J37/305 , H01L21/027 , H01L21/3065 , H01L21/30
摘要： PURPOSE:To contrive the improvement of processing by inducing reactive gas or gas plasma in a sample chamber in performing fine processing by aiming a charged beam at a processed substance. CONSTITUTION:A charged beam 2 taken out of a charged beam generating chamber 1, for example, a CF3 ion is accelerated at 200-300V and etching is performed by aiming the charged beam 2 at a sample 4 to be processed, for example, Si. At that time, the gas pressure in a sample chamber 3 is maintained at about 1-10 Pas. As the result, a decrease in etching speed is not recognized. And the etching speed can be further increased by aiming an electromagnetic wave 7, for example, infrared rays, at the sample 4 to be processed from an electromagnetic waves generator 8. Furthermore, even if a processing material is changed, fine processing can be done by materials except Si if a suitable charged beam and gas or plasma, electromagnetic wave permitting etching for the material by sublimation or evaporation are selected.

77. 发明专利

JPS5732378A Plasma etching apparatus 失效
标题翻译：等离子体蚀刻装置
公开(公告)号：JPS5732378A
公开(公告)日：1982-02-22
申请号：JP10752580
申请日：1980-08-05
申请人： Mitsubishi Electric Corp
发明人： ITAKURA HIDEAKI , ABE HARUHIKO , KONISHI KANJI
IPC分类号： C23F4/00 , C23F1/08 , H01L21/302 , H01L21/3065
摘要： PURPOSE: To inhibit a surface temp. rise of products to be worked due to heat of reaction and to prevent the deformation and deterioration of a resist by cooling the products when they are present in the open region of a sample electrode set opposite to a high frequency electrode.
CONSTITUTION: To restrict the generation region of gas plasma 7 a high frequency electrode 24 in a reactor 1 is regulated in size so that it is opposite to about half of a sample electrode 25. Accordingly, products 8 to be worked present in the region of the electrode 25 opposite to the electrode 24 are etched, and products 8 to be worked present in the other region not opposite to the electrode 24 are not exposed to gas plasma 7. Since the electrode 25 is rotated with a rotating mechanism 9, the products 8 are alternately subjected to the progress and stop of etching. As a result, a surface temp. rise of the products 8 during etching and the thermal deformation and deterioration of a resist due to the temp. rise can be inhibited, so micropattern can be formed without causing deformation.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：抑制表面温度。由于反应热而被加工的产品的升高，并且当产品存在于与高频电极相对的样品电极的开放区域中时，通过冷却产品来防止抗蚀剂的变形和劣化。构成：为了限制气体等离子体7的产生区域，反应器1中的高频电极24的尺寸被调节成与样品电极25的大约一半相反。因此，待加工的产品8存在于蚀刻与电极24相对的电极25，而与电极24不相对的另一区域中的待加工制品8不暴露于气体等离子体7.由于电极25通过旋转机构9旋转，所以产品 8交替地进行蚀刻的进行和停止。因此，表面温度在蚀刻期间产品8的上升和由于温度导致的抗蚀剂的热变形和劣化。可以抑制上升，因此可以形成微图案而不引起变形。

78. 发明专利

JPS56158432A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS56158432A
公开(公告)日：1981-12-07
申请号：JP6430780
申请日：1980-05-12
申请人： MITSUBISHI ELECTRIC CORP
发明人： ABE HARUHIKO , HARADA HIROJI , TSUBOUCHI NATSUO
IPC分类号： H01L23/522 , H01L21/316 , H01L21/768 , H01L23/29 , H01L23/31
摘要： PURPOSE:To prevent an erroneous operation caused by an alpha-ray by providing a tantalum oxide film or a tungsten oxide film through Si3N4 or directly on a circuit element and a wiring layer on the semiconductor substrate. CONSTITUTION:In the MOSLSI memory, further a tantalum oxid film 10 is formed on the whole surface of the Si3N4 film 9. Because the shielding capacity of the radioactive rays such as an alpha-ray is the higher the atomic weight is larger and the atomic weight of tantalum is large by that much, the film 10 of about 1mum has the capacity larger than a polyamide resin of about 30mum. As tantalum oxide is an insulator, it can be directly laminated. As tungsten has the approximate atomic weight to that of tantalum, the tungsten oxide film is equally effective for the same purpose.

79. 发明专利

JPS5679473A PREPARING METHOD OF METAL GATE FILM 失效
公开(公告)号：JPS5679473A
公开(公告)日：1981-06-30
申请号：JP15650779
申请日：1979-11-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： NAGATOMO MASAO , TSUBOUCHI NATSUO , ABE HARUHIKO , HARADA HIROJI , MIHASHI JIYUNICHI
IPC分类号： H01L21/28 , H01L29/78
摘要： PURPOSE:To obtain a gate film through a self-matching by setting a metal layer upon a ground layer including Si and performing a self-matching with metalic siliconized layer and the ground layer. CONSTITUTION:A poly-silicon ground layer 3 is selectively formed upon SiO2 film 2 of an Si substrate 1 to set to an Mo 4 thereon. When a LASER 6 is irradiated to heat it approximately at 1,000 deg.C, only Mo 4 on poly-silicon 3 becomes siliconized material 5. Then, when unreacted Mo 4 is etched, a gate film is obtained by self- matching and closely contacted with the ground layer.

80. 发明专利

JPS5679453A PRODUCTION OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5679453A
公开(公告)日：1981-06-30
申请号：JP15650879
申请日：1979-11-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： ABE HARUHIKO , MIHASHI JIYUNICHI , TSUBOUCHI NATSUO , HARADA HIROJI , NAGATOMO MASAO
IPC分类号： H01L21/316 , H01L21/302 , H01L21/3065
摘要： PURPOSE:To facilitate a finer pattern by employing a high-melting-point metal able to sublimate by oxidation for a mask for obtaining a thin oxide film. CONSTITUTION:A resist mask 4 is used for SiO2 2 on an Si substrate 1 to make an Mo 3. After the removal of the mask 4, Mo 3 undergoes thermal oxidation at a high temperature to be converted MoO2 5 being gradually sublimated away. On the other hand, with Mo 3 as mask, a thick oxide film 6 is formed in other parts. In this manner, as Mo 3 is sublimated away completely through oxidation, a fine hole is allowed to be formed surrounded by the thick oxide film 6. Smaller crystal particle size of Mo enables formation of a finer pattern than a mask of Si3N4. Beside Mo, W may be used.

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