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1. 发明专利

JPS6098679A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6098679A
公开(公告)日：1985-06-01
申请号：JP20695483
申请日：1983-11-02
申请人： MITSUBISHI ELECTRIC CORP
发明人： MIHASHI JIYUNICHI , MATSUKAWA TAKAYUKI , WATAKABE YAICHIROU
IPC分类号： H01L21/265 , H01L21/268 , H01L29/78
摘要： PURPOSE:To selectively anneal only a gate oxide film by a method wherein annealing for recovery from the damage of the gate oxide film is performed by irradiation with laser beams having a wavelength showing the absorption peak of the gate oxide film. CONSTITUTION:After exposure with charged particles P, laser annealing is performed to remove the trap level. At this time, a semiconductor substrate 1 is an Si substrate; therefore its gate oxide film 2 is of SiO2, and the wavelength of the laser beam L is set at about 9.3mum so as to be at the absorption peak of SiO2. This beam is hardly absorbed to the substrate, but absorbed most in the SiO2. Therefore, the film 2 comes to higher temperatures, and fixed charges and the trap level are annealed out.

2. 发明专利

JPS6021537A TESTING METHOD OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6021537A
公开(公告)日：1985-02-02
申请号：JP13001583
申请日：1983-07-15
申请人： MITSUBISHI ELECTRIC CORP
发明人： MIHASHI JIYUNICHI , MATSUKAWA TAKAYUKI
IPC分类号： G01R31/26 , G01R31/28 , G01R31/302 , H01L21/66
摘要： PURPOSE:To realize the test for semiconducltor device within a short period with a high accuracy by executing logic test by scanning each gate array to which the logic pattern is input with the primary electron beam sent from the scanning type electron microscope which makes strobe operation. CONSTITUTION:At the time of logic test of LSI chip, the specified logic pattern obtained from a logic pattern generator is input to the input side electrode extracting part 2a with a multi-pin probe and front and rear positions 4 of n-stage gate array 3 are scanned for (n) times with the primary electron beam of strobe SEM. The signal lines of front and rear positions 4 of the gate array 3 can be extracted as the secondary signal. The logic test of internal gate of each gate array 3 can be conducted by comparing such logic map with that of reference LSI and all internal gates can be tested.

3. 发明专利

JPS5679450A ELECTRODE AND WIRING OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5679450A
公开(公告)日：1981-06-30
申请号：JP15650679
申请日：1979-11-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： TSUBOUCHI NATSUO , ABE HARUHIKO , NAGATOMO MASAO , HARADA HIROJI , MIHASHI JIYUNICHI
IPC分类号： H01L29/78 , H01L21/3205 , H01L23/482 , H01L23/52 , H01L29/45
摘要： PURPOSE:To lower the resistivity of an electrode and a wiring by sandwitching a high-melting point metal layer made of Mo, W or the like with two layers of polycrystalline Si while Ti layer is interposed therebetween for better adhesivity when the electrode or the wiring of a semiconductor device is formed. CONSTITUTION:When an electrode or a wiring is formed on a ground substrate 1, initially a polycrystalline Si layer 2 is entirely grown in the gaseous phase and then, a Ti layer 3 is applied thereon. Then, a Mo layer 4 and again a Ti layer 5 are formed on the layer 3 and then a polycrystalline Si layer 6 is grown in the gaseous phase on the top-most layer. Thereafter, with a resist as mask, the layers are treated in a gas plasma of CF4 by photolithography to remove unnecessary parts selectively. In this manner, the resistivity of the electrode wiring can be lowered employing the doping of impurities and a well self-matching polycrystalline Si. Or it may be accepted to wrap the polycrystaline Si with these high-melting point metals.

4. 发明专利

JPS60235423A SEMICONDUCTOR MANUFACTURING APPARATUS 失效
公开(公告)号：JPS60235423A
公开(公告)日：1985-11-22
申请号：JP9348284
申请日：1984-05-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHIMIZU MASAHIRO , MIHASHI JIYUNICHI
IPC分类号： H01L21/30 , G03F7/20 , H01L21/027
摘要： PURPOSE:To secure a wafer so that the plane thereof is perpendicular to light rays regardless of any possible warpage of the wafer, by employing an electrostatic wafer chuck. CONSTITUTION:An electrostatic chuck 7 secures a wafer 3 thereon by means of electrostatic force so that the plane of the wafer 3 is perpendicular to light rays 1. This is effected because the electrostatic force is sufficiently strong, and the wafer 3 can be retained in this state even if it has warpage. The wafer 3 is removed by blowing air against it through air holes 6. Since the chuck 7 reliably secures the wafer 3 so that the plane thereof is perpendicular to the light rays, there is no offset of focal point within the wafer 3, so that it is possible to increase the production yield.

5. 发明专利

JPS59224173A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS59224173A
公开(公告)日：1984-12-17
申请号：JP9965683
申请日：1983-06-03
申请人： MITSUBISHI ELECTRIC CORP
发明人： MATSUKAWA TAKAYUKI , MIHASHI JIYUNICHI
IPC分类号： H01L29/78
摘要： PURPOSE:To prevent poor insulation, by using an anisotropic plasma etching method, coating the end part of a gate with an insulator by a self-aligning manner, and providing a large interval between a metal silicide layer at a gate part and a metal silicide layer at the parts of a source and a drain. CONSTITUTION:Ions of impurities having a reverse conducting type with respect to a silicon substrate 1 are implanted in the surface of gate polysilicon under the state a pattern formation has been completed. Thus a shallow impurity layer 8 is formed. An insulator layer 9 made of silicon oxide and the like is formed on the entire surface. The insulator layer is removed by an anisotropic plasma etching method, and the end part of the gate polysilicon 4 is made to remain so as to form an edge. Then a high melting point metal layer 5 is attached to the entire surface, and sintering is performed in a high temperature atmosphere at 800 deg.C or more. Then, a metal silicide film 6 is formed only on the surface of the gate polysilicon 4 and the parts of a source and a drain.

6. 发明专利

JPS59132141A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59132141A
公开(公告)日：1984-07-30
申请号：JP701983
申请日：1983-01-17
申请人： Mitsubishi Electric Corp
发明人： MATSUKAWA TAKAYUKI , MIHASHI JIYUNICHI
IPC分类号： H01L21/316 , H01L21/32 , H01L21/76 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76 , H01L21/76202 , H01L21/7621
摘要： PURPOSE: To realize an isolation oxide film, the surface thereof is flat and in which there is no bird-beak, by etching a semiconductor substrate, coating the side surface of the substrate with a silicon nitride film and forming the isolation oxide film.
CONSTITUTION: Silicon substrates 1 in sections to which isolation oxide films 6 must be formed previously are etched to form hole sections 8 in predetermined depth, and the side surfaces of the hole sections 8 are also coated with a silicon nitride film 3 to prevent the progress of an oxidation in the side surfaces. The oxide films 6 formed take a section shape in which there is hardly bird-beak. When the etching depth of the substrate 1 is selected so as to approximately coincide with the thickness of the oxide film 6, a flat isolation in approximately the same surface of the surface of the isolation oxide film and the surface of the substrate in an active region is enabled.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了实现隔离氧化膜，其表面是平坦的，其中不存在鸟嘴，通过蚀刻半导体衬底，用氮化硅膜涂覆衬底的侧表面并形成隔离氧化物膜。构成：预先形成隔离氧化膜6的部分中的硅衬底1被蚀刻以形成预定深度的孔部8，并且孔部8的侧表面也涂有氮化硅膜3以防止进行的侧表面氧化。所形成的氧化膜6呈几乎没有鸟嘴状的截面形状。当选择衬底1的蚀刻深度以与氧化膜6的厚度大致一致时，在隔离氧化膜的表面的大致相同的表面和有源区中的衬底的表面上的平坦隔离启用。

7. 发明专利

JPS5679433A FORMING OF ULTRA FINE PATTERN 失效
公开(公告)号：JPS5679433A
公开(公告)日：1981-06-30
申请号：JP15650579
申请日：1979-11-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： ABE HARUHIKO , TSUBOUCHI NATSUO , NAGATOMO MASAO , HARADA HIROJI , MIHASHI JIYUNICHI
IPC分类号： H01L21/3213 , H01L21/302 , H01L21/3065
摘要： PURPOSE:To facilitate the forming of an ultra fine pattern by a method wherein Mo film is coated on a base layer when the ultra fine pattern electrode is formed on a semiconductor, antioxide film layer is made on the film in accordance with the pattern to be left, heat treated in an oxidation atmosphere to sublimate the Mo film in the exposed area. CONSTITUTION:Mo film layer 2 is coated on a surface of the base layer 1, anitoxide film 3 such as Al film, Si3N4 film SiO2 film etc. is arranged in accordance with the desired pattern, heat treated at a temperature higher than 400 deg.C in the atmosphere of O2 of which pressure is decreased or increased, and the Mo film 2 in the exposed area is changed to the film 4 such as MoO2, MoO3 etc. Similarly, the sublimation of the film 4 is used to sublimate the same to keep the Mo film 2 of ultra fine pattern only below the film 3. With this arrangement, regardless of the material quality of the base layer, a forming of the ultra fine pattern can be facilitated.

8. 发明专利

JPS5410690A PHOTO DETECTOR 失效
公开(公告)号：JPS5410690A
公开(公告)日：1979-01-26
申请号：JP7582077
申请日：1977-06-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： MIHASHI JIYUNICHI , KOTANI KIYOUHIKO , KAWAZU SATORU
IPC分类号： G03B7/081 , G01J1/44 , H01L31/10 , H01L31/18
摘要： PURPOSE:To obtain a photo detector of which photo detector surface may be small in size, easily permitting to redcue the scale of the entire device including such photo detector, and which can obtain a delay time corresponding to the quantity of light received with a simple circuit suitable for use in an automatic exposure control.

9. 发明专利

JPS59132142A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59132142A
公开(公告)日：1984-07-30
申请号：JP805183
申请日：1983-01-18
申请人： Mitsubishi Electric Corp
发明人： MIHASHI JIYUNICHI , MATSUKAWA TAKAYUKI
IPC分类号： H01L21/76 , H01L21/31 , H01L21/762
CPC分类号： H01L21/76208
摘要： PURPOSE:To form a flat inter-element isolation oxide film, in which there is no bird-beak, by forming a meshy or striped slit to an isolation region section in a semiconductor substrate through etching and forming the isolation oxide film through oxidation. CONSTITUTION:A resist film 4 is formed on the surface of a semiconductor substrate 1, and an isolation region 9 is patterned according to a necessary manner while an active region 6 is left as it is in the film 4. The substrate 1 is etched while using the pattern 4 as a mask. An oxide film 10 is formed in the active region 6 and an oxide film 11 in the isolation region 9 through oxidation. The thermal oxide film is removed through etching only by the thickness of the film 10 generated in the region 6, and an isolation oxide film 11a is left in the region 9.
摘要翻译：目的：通过在半导体衬底中通过蚀刻和形成隔离氧化膜形成半导体衬底中的隔离区段，形成不具有鸟嘴的平坦的元件间隔离氧化膜。构成：在半导体衬底1的表面上形成抗蚀剂膜4，并且在活性区域6原样保留在膜4中的同时，根据必要的方式对隔离区域9进行图案化。基板1被蚀刻同时使用图案4作为掩模。通过氧化，在有源区域6和隔离区域9中形成氧化膜11。通过仅通过蚀刻区域6中产生的膜10的厚度的蚀刻去除热氧化膜，并且在区域9中留下隔离氧化物膜11a。

10. 发明专利

JPS58204551A Positioning mechanism for semiconductor substrate 失效
标题翻译：半导体基片定位机理
公开(公告)号：JPS58204551A
公开(公告)日：1983-11-29
申请号：JP8746582
申请日：1982-05-21
申请人： Mitsubishi Electric Corp
发明人： MIHASHI JIYUNICHI , FUKUMOTO HAYAAKI , MIZUGUCHI KAZUO , HATSUTA MUNEO , WAKAMIYA WATARU , YONEDA MASAHIRO
IPC分类号： H01L21/68
CPC分类号： H01L21/681
摘要： PURPOSE:To position the oriented flat part (OF) of a semiconductor substrate at the prescribed position in a short time by providing the flat part of a detecting plate at the position to set the OF position of the substrate, placing the substrate on a base, rotating it and detecting the OF of the substrate from the maximum point of the detected light output. CONSTITUTION:A semiconductor substrate 1 is positioned at the part corresponding to a detecting plate 12 on a base 10, a lamp 14 is energized, the light is focused via a lens 22, and received by a photodetector 23. The plate 12 is rotated by a pulse motor 1 to match the OF1a of the substrate 1 to the set position. Then, the base 10 which places the substrate 1 at the part corresponding to the plate 12 is rotated by a pulse motor 19. When the flat parts 1, 12a are coincident to one another, the superposed shape of the substrate 1 and the plate 12 becomes minimum, and the received light quantity of the detector becomes maximum. The OF1a of the substrate 1 is detected from the rotating angle theta of the base 10, thereby readily positioning the substrate at the prescribed position.
摘要翻译：目的：通过在检测板的平坦部分设置基板的OF位置的位置处，在短时间内将半导体基板的定向平坦部分（OF）定位在规定位置，将基板放置在基座从所检测的光输出的最大点旋转并检测衬底的OF。构成：半导体基板1位于与基座10上的检测板12对应的部分，灯14通电，光被透镜22聚焦，并由光电检测器23接收。板12旋转脉冲电机1将基板1的OF1a与设定位置相匹配。然后，将基板1放置在与板12对应的部分的基座10通过脉冲电动机19旋转。当平坦部分1,12a彼此重合时，基板1和板12的重叠形状变得最小，并且检测器的接收光量变为最大。从基座10的旋转角θ检测基板1的OF1a，从而容易地将基板定位在规定位置。

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