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71. 发明专利

JPH09116120A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH09116120A
公开(公告)日：1997-05-02
申请号：JP26673995
申请日：1995-10-16
申请人： HITACHI LTD
发明人： KATO MASATAKA , ADACHI TETSUO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To realize highly reliable novel electrical rewriting with high density by connecting well areas in a memory cell on the same array with each other through a well line and providing a means for supplying voltage to the well area individually every column. SOLUTION: Memory cells for three bits are formed on a silicon oxide film 102. Every memory cell is electrically isolated from each other through a silicon oxide film 104. In addition, a drain area 107 and a source area 108 are formed with a well area 103 in between, and every area has a depth of 0.1 to 0.3μm. A p-type impurity area 112 reduces the breakdown voltage of a joint part between the areas 108 and 103 and eases writing operation thereof. A word line functions as a control gate to delete/write/read data for respective memory cells.

72. 发明专利

JPH0991978A NONVOLATILE SEMICONDUCTOR MEMORY AND COMPUTER SYSTEM EMPLOYING IT 失效
公开(公告)号：JPH0991978A
公开(公告)日：1997-04-04
申请号：JP25240095
申请日：1995-09-29
申请人： HITACHI LTD
发明人： TANAKA TOSHIHIRO , KATO MASATAKA , ADACHI TETSUO
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To obtain a nonvolatile semiconductor memory having enhanced rewrite resistance and a computer system employing it. SOLUTION: Rewriting operation continues only for such memory cell as the threshold voltage has not yet reached the verify word line voltage after finishing the rewriting (write, erase) operation. Since the threshold voltage of memory cell can be matched on the writing side and erasing side, total quantity of charges to be passed through an insulation film can be reduced at the time of rewriting operation and the rewriting resistance can be enhanced.

73. 发明专利

JPH0935486A SEMICONDUCTOR NONVOLATILE MEMORY AND COMPUTER SYSTEM EMPLOYING IT 失效
公开(公告)号：JPH0935486A
公开(公告)日：1997-02-07
申请号：JP17524195
申请日：1995-07-11
申请人： HITACHI LTD
发明人： TANAKA TOSHIHIRO , KATO MASATAKA , KIMURA KATSUTAKA , OSHIMA KAZUYOSHI , MIYAZAWA KAZUYUKI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor nonvolatile memory in which noise resistance and disturb resistance can be enhanced through a reciprocal bit line/sense latch system by matching the layout of sense latch circuit and the pitch of bit line of memory cell. SOLUTION: An EEPROM is constituted of a plurality of memory mats comprising transistors having electrically rewritable threshold value wherein two sense latch circuits SL1-SLn are disposed on the opposite sides of respective memory mats for two bit lines B1-Bn. Data can be inputted/outputted for the memory mat from the opposite sides thereof through a column gate array circuit connected with sense latch circuits SL1-SLn. Read and verify operations are carried out based on the parity of bit lines B1-Bn and flush write operation is carried out regardless of the parity of bit lines B1-Bn.

74. 发明专利

JPH08162546A NONVOLATILE SEMICONDUCTOR MEMORY AND ITS MANUFACTURE 失效
公开(公告)号：JPH08162546A
公开(公告)日：1996-06-21
申请号：JP30452994
申请日：1994-12-08
申请人： HITACHI LTD
发明人： KOBAYASHI TAKASHI , KATO MASATAKA , USHIYAMA MASAHIRO , ADACHI TETSUO
IPC分类号： H01L21/8247 , H01L29/788 , H01L29/792
摘要： PURPOSE: To provide a nonvolatile semiconductor memory which can relax field concentration to a layer insulation film between a floating gate electrode and a control gate electrode and improve high integration and charge holding property, and a manufacturing method thereof. CONSTITUTION: As a layer insulation film between a control gate electrode and a floating gate electrode 204 consisting of a polycrystalline Si film, a single layer of an SiO2 film 205 formed by a CVD method is used. Since a film thickness (b) of an SiO2 film 205 on an upper end part of the floating gate electrode 204 is thereby larger than a film thickness (a) on an upper surface, field concentration in an upper end part is relaxed and charge holding characteristic is improved. Furthermore, since a CVD method can be executed at a lower temperature than a conventional ONO film formation method, high integrated can be realized.

75. 发明专利

JPH08138385A OPERATION METHOD FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH08138385A
公开(公告)日：1996-05-31
申请号：JP27332794
申请日：1994-11-08
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： SATO SATOHIKO , KATO MASATAKA , MIYAMOTO NAOKI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06
摘要： PURPOSE: To obtain a control system for nonvolatile semiconductor memory device in which electric rewriting can be carried out reliably at high rate. CONSTITUTION: When information is written in a floating gate type nonvolatile memory cell or the information is erased therefrom, a writing or erasing voltage is split into a plurality of voltage pulses including at least one voltage pulse having a rising time different from those of other voltage pulses. Rising of voltage pulse is made gentle immediately after starting the writing operation and a switching is made to a steep voltage pulse in the way thus preventing excess rewriting of high rate bit while allowing high rate writing of low rate bit. Furthermore, a voltage pulse rising slowly is applied immediately after starting the rewriting operation in order to relax stress being applied to a gate insulation film thus prolonging the lifetime of a memory cell.

76. 发明专利

JPH0869698A MEMORY SYSTEM 失效
公开(公告)号：JPH0869698A
公开(公告)日：1996-03-12
申请号：JP22878094
申请日：1994-08-30
申请人： HITACHI LTD
发明人： SASAKI TOSHIO , KATO MASATAKA , ADACHI TETSUO , TANAKA TOSHIHIRO , KUME HITOSHI , KIMURA KATSUTAKA
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115
摘要： PURPOSE: To provide a memory system efficiently rewritable without retreating the data in an erase area at a rewriting time. CONSTITUTION: Memory chips CH1-CHk capable of simultaneously writing the data in plural pieces of memory cells on one word line by using a sense latch circuit, and an interface means 100 interfacing them with the outside are adopted, and one word line is defined one sector similarly to erasure, and the write in sector is attained. Since the unit of the write coincides with the same of the erasure, the temporarily keeping work of the data required when the data are rewritten and a retreat area for it are eliminated.

77. 发明专利

JPH06244433A SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06244433A
公开(公告)日：1994-09-02
申请号：JP2645893
申请日：1993-02-16
申请人： HITACHI LTD
发明人： HISAMOTO MASARU , KIMURA SHINICHIRO , NODA HIROMASA , KATO MASATAKA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To provide a semiconductor memory having floating gates and control gates, in which the ratio of the capacitance between the control gate and the floating gate to the capacitance between the floating gate and channel is increased by forming the floating gates over bit lines. CONSTITUTION:Bit lines are formed in a laminated structure of a heavily-doped polysilicon conductor layer 200 and a tungsten silicide layer 205. A substrate includes a diffused layer 210 that overlaps the bit lines. Floating gate 520 are arranged between and over the bit lines. Therefore, the bottom area of the floating gate depends on the spacing between bit lines, and thus the gate becomes much smaller than side spacers. On the other hand, the top of the floating gate is large independent of the bottom area because it extends over the bit lines.

78. 发明专利

JPH06177392A MANUFACTURE OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH06177392A
公开(公告)日：1994-06-24
申请号：JP33140292
申请日：1992-12-11
申请人： HITACHI LTD
发明人： ADACHI TETSUO , KATO MASATAKA , TANAKA TOSHIHIRO , SASAKI TOSHIO , KUME HITOSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To provide an electrically rewritable nonvolatile semiconductor storage device which is reduced in cell area by preventing the biting of a bird's beak into a tunnel oxide film and its manufacturing method. CONSTITUTION:The method for manufacturing a nonvolatile storage device provided with a floating gate electrode 3 formed on a semiconductor substrate 1 with a gate insulating film 2 in between, control gate electrode 5, and source and drain areas contains a process for forming the electrode 3, process for forming an insulating film on the side wall of the electrode 3, and process for forming an insulating film on the surface of the substrate 1 by using the insulating film formed on the side wall of the electrode 3 as an oxidation resisting film. Therefore, the biting of a bird's beak into a tunnel oxide film below a floating gate due to an oxidizing process can be prevented. Since the thickness of the gate oxide film does not become thicker, writing and erasing operations can be performed at high speeds without being restricted by the above-mentioned processes.

79. 发明专利

JPH06119773A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH06119773A
公开(公告)日：1994-04-28
申请号：JP26717792
申请日：1992-10-06
申请人： HITACHI LTD
发明人： TAKEUCHI MIKI , KATO MASATAKA , MATSUNO KATSUMI , NAKAGOME YOSHINOBU , AOKI MASAKAZU
IPC分类号： G11C11/22 , G11C11/401 , G11C14/00 , G11C17/04 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108
摘要： PURPOSE:To obtain a high speed and highly integrated memory cell with high reliability by connecting a ferroelectric substance capacitor and a paraelectric substance capacitor in series and impressing a prescribed fixed voltage. CONSTITUTION:This memory is constituted so that the paraelectric substance capacitor CO and the ferroelectric substance capacitor CFE whose insulation film is made from ferroelectric substance are connected in series, and voltage in a connection node VN is detected by a voltage monitor. In information writing operation, the voltage VIS is impressed to a terminal V1, and the transition of two voltage stable points VN0, VN1 occurring in the VN is performed by making the impressed voltage in the V1 VIS to and from V1L, and write is executed. Further, in reading operation, though the voltage in the node VN is detected by the voltage monitor circuit and read is executed, at this time, since inversion in the polarization of the CFE is unnecessitated, the voltage in the V1 is made the fixed voltage inducing no polarization. Thus, delay in read due to the inversion in the polarization is eliminated, and fatigue in the ferroelectric substance film is suppressed, and the voltage is obtained regardless of the area of the capacitor, and high integration is obtained.

80. 发明专利

JPH0694787A HIGHLY RELIABLE INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0694787A
公开(公告)日：1994-04-08
申请号：JP24295292
申请日：1992-09-11
申请人： HITACHI LTD
发明人： AOKI MASAAKI , KATO MASATAKA
IPC分类号： G01R31/26 , G01R31/28 , H01L27/14
摘要： PURPOSE:To accurately grasp the exposure dose of a chip and to enable the highly reliable control of the chip by providing a circuit for detecting an exposure dose and performing the detection of the exposure dose by the detection of the noise of an MOS transistor. CONSTITUTION:An exposure dose detection part 203 contains a MOS transistor 21, a gate voltage power supply 22, a drain voltage power supply 23 and a load resistor 24 to be built in a highly reliable integrated circuit chip. The detection signal of the exposure dose detection part is subjected to signal processing through a low noise operational amplifier 25, a BPC 26 and a DC voltmeter 27 and an output signal 28 is outputted. The output signal 28 displays not only the noise value of the exposed MOS transistor 21 but also the exposure dose thereof. A comparator 201 compares the reference value of a reference signal source 29 giving a tolerant noise value with the noise value of the output signal 28 to inform whether the noise value of the output signal 28 exceeds the reference value of the signal source 29 to a user by an output signal 202. By this constitution, an exposure dose can be detected with high sensitivity by detecting the noise of the MOS transistor 21.

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