专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明专利

JPS5763857A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5763857A
公开(公告)日：1982-04-17
申请号：JP13948380
申请日：1980-10-03
申请人： Mitsubishi Electric Corp
发明人： YAMAUCHI MASAHIDE
IPC分类号： H01L21/8238 , H01L21/331 , H01L23/58 , H01L27/092 , H01L29/72 , H01L29/73
CPC分类号： H01L29/72
摘要： PURPOSE:To obtain a semiconductor device having durability against overcurrent without damaging a gain, by incorporating in the device an element which bypasses input current only when temperature rises. CONSTITUTION:A transistor Q wherein an n type semiconductor layer 2 is a collector, a p type region 3 is a base and an n type resion 5 is emitter is formed. Moreover, in the other part of the n type semiconductor layer 2, a p type region 10, an n type region 11 and a p type region 12 are formed, an element CR having the characteristic of a thermal thyristor is thereby constituted, and the p type region 12 is connected with the base region 3 and the p type region 10 with the emitter region 5. When the temperature of the transistor rises, the thermal thyristor connected in parallel to a base input is turned conductive and bypasses input current, whereby the breakage of the semiconductor device is prevented.
摘要翻译：目的：为了获得具有耐过电流而不损坏增益的半导体器件，通过在器件中仅在温度升高时旁路输入电流的元件。构成：其中n型半导体层2是集电极，p型区域3是基极并且形成n型晶胞5是发射极的晶体管Q。此外，在n型半导体层2的另一部分中，形成ap型区域10，n型区域11和ap型区域12，由此构成具有热晶闸管特性的元件CR，并且p型区域12与基极区域3和p型区域10与发射极区域5连接。当晶体管的温度上升时，与基极输入并联连接的热晶闸管导通并绕过输入电流，由此断开防止了半导体器件。

62. 发明专利

JPS5756967A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5756967A
公开(公告)日：1982-04-05
申请号：JP13201880
申请日：1980-09-22
申请人： Nec Corp
发明人： TSUDA HIROSHI
IPC分类号： H01L29/43 , H01L21/225 , H01L21/28 , H01L21/331 , H01L29/72 , H01L29/73
CPC分类号： H01L29/72
摘要： PURPOSE:To prevent the shortcircuit between the emitter E and the base B of a transistor of miniature size by forming an electrode window in a mask layer made of an oxidized film and a nitrided film, forming a doped polysilicon layer over the emitter window, and then removing a nitrided film. CONSTITUTION:An oxidized film 13 and a nitrided film 30 are formed on a substrate formed with a base layer 12 in a step of formig a transistor of DOPOS type, and holes are opened at an emitter window 14 and a base contact window 15. Then, an As-doped polysilicon layer 16 and an oxidized film 17 are, for example, accumulated, and are photoetched to cover the window 14 and to pattern it. Then, the film 30 is removed in thermal phosphoric acid, is treated by supersonic wave, and the layer 16 and the oxidized film are retained only in the window 14. Subsequently, with the polysilicon 16 as a diffusion source, an emitter diffused layer is formed, the oxidized film 16 is removed, and a metallic electrode is formed. Thus, the structure in which the interval of the electrodes formed on the base contact and the polysilicon layer is reduce can be readily formed, and the shortcircuit between the electrodes can be prevented, and the characteristics and the yield can be improved.
摘要翻译：目的：通过在由氧化膜和氮化膜构成的掩模层中形成电极窗，在发射极窗口上形成掺杂多晶硅层，以防止发射极E与微型尺寸晶体管的基极B之间的短路，以及然后除去氮化膜。构成：在形成DOPOS型晶体管的步骤中，在形成有基极层12的基板上形成氧化膜13和氮化膜30，并且在发射极窗口14和基底接触窗口15处开孔。然后例如，As掺杂多晶硅层16和氧化膜17被累积，并被光刻以覆盖窗口14并对其进行图案化。然后，在热磷酸中除去膜30，用超声波处理，层16和氧化膜仅保留在窗口14中。随后，以多晶硅16作为扩散源，发射极扩散层为形成，除去氧化膜16，形成金属电极。因此，可以容易地形成其中形成在基极触点上的电极的间隔和多晶硅层的间隔的结构，并且可以防止电极之间的短路，并且可以提高特性和产量。

63. 发明专利

JPS5756966A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5756966A
公开(公告)日：1982-04-05
申请号：JP13127580
申请日：1980-09-20
申请人： Fujitsu Ltd
发明人： INAYOSHI KATSUYUKI
IPC分类号： H01L29/73 , H01L21/316 , H01L21/331 , H01L21/76 , H01L21/8222 , H01L27/06 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To self align the steps of manufacturing a walled emitter structure, to improve the integration of and the speed of the operation of a semiconductor device and to equalize the characteristics of the device by forming an oxidized film pattern on the nitride film of base and emitter electrode forming window forming regions. CONSTITUTION:An isolation layer 35 is formed in a P type substrate 31 formed with buried layer 32 and an N type epitaxial layer 34, an oxidized film 36 and a nitrided film 37 are then laminated, and oxidized film pattern 38 is formed on the nitrided film 37 of the region formed with the respective electrode windows. Then, a resist 39 is covered between the base and the emitter windows, the nitride film 37 is selectively remoed, the resist 39 is removed, and the selectively oxidezed film 42 is then formed. Then, the collector window 37C is covered, B ions are injected, are oxidized to form an oxidized film 45 and a base region 46. Then, the film 37 and the film 36 are removed, with the resist 52 as a mask an emitter region 49 and a collector connecting point 51 are injected with ions, and the resist 52 is then removed, is heat treated, and a structure exposed with the diffused layers 64, 54, 55 is formed in the respective electrode windows. Thus, the electrode connecting points of a bipolar device which is decreased in size and is increased in density can be self-aligned.
摘要翻译：目的：为了自动对准制造壁式发射极结构的步骤，提高半导体器件的集成度和操作速度，并通过在基底的氮化物膜上形成氧化膜图案来平衡器件的特性，以及发射电极形成窗口形成区域。构成：在形成有掩埋层32的P型基板31中形成隔离层35，然后层叠N型外延层34，氧化膜36和氮化膜37，在氮化层上形成氧化膜图案38 形成有各个电极窗的区域的膜37。然后，在基底和发射窗之间覆盖抗蚀剂39，选择性地除去氮化物膜37，除去抗蚀剂39，然后形成选择性氧化膜42。然后，收集器窗口37C被覆盖，B离子被注入，被氧化以形成氧化膜45和基底区域46.然后，除去膜37和膜36，以抗蚀剂52作为掩模，发射极区域 49和集电极连接点51注入离子，然后去除抗蚀剂52，进行热处理，并且在各个电极窗中形成暴露于扩散层64,54,55的结构。因此，尺寸减小并且密度增加的双极器件的电极连接点可以是自对准的。

65. 发明专利

JPS5735370A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5735370A
公开(公告)日：1982-02-25
申请号：JP11060180
申请日：1980-08-12
申请人： Nec Corp
发明人： AOMURA KUNIO
IPC分类号： H01L29/43 , H01L21/28 , H01L21/331 , H01L29/72 , H01L29/73
CPC分类号： H01L29/72
摘要： PURPOSE:To reduce the base resistance by connecting a metal silicide layer provided on the surface of an inactive base region to an external eletrode through a hole part in an insulting film. CONSTITUTION:The device is constituted by an N type collector region 11, a P type ba region 12, an N type emitter region 13, and external electrode 17 and 17' in said regions. A platinum silicide layer 15 is provided on the surface of the base region 12, and the resistance from the external electrode 17 for the base on the hole provided in the insulating film 16 to the emitter region 13 is decreased.
摘要翻译：目的：通过将设置在非活性基底区域的金属硅化物层与绝缘膜上的孔部分的外部电极连接来降低基极电阻。构成：该装置由所述区域中的N型集电极区域11，P型区域12，N型发射极区域13和外部电极17和17'构成。在基极区域12的表面上设置有铂硅化物层15，并且从设置在绝缘膜16上的孔的基极的外部电极17的电阻降低到发射极区域13。

66. 发明专利

JPS5731173A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5731173A
公开(公告)日：1982-02-19
申请号：JP10663980
申请日：1980-08-01
申请人： Sanyo Electric Co Ltd , Tokyo Sanyo Electric Co Ltd
发明人： TANAKA TADAHIKO , NOZAKI TSUTOMU
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8222 , H01L29/72 , H01L29/73
CPC分类号： H01L29/72
摘要： PURPOSE:To determine an arbitary and large value of an emitter resistance without being limited by the composition of an emitter, by a method wherein the emitter and the emitter resistance are made independent each other by taking the emitter electrode out of a semiconductor substrate and composing the emitter resistance with the substrate. CONSTITUTION:A P layer 110 and an epitaxial layer 111, which is piled on the layer 110, compose a substrate 11. The layer 111 is utilized as an emitter resistance and its value is arbitrarily determined at a value not more than 100ohms by controlling the specific resistivity and the thickness. An N buried layer 12 is provided and an epitaxial layer 13 is piled over it. The epitaxial layer 13 is devided by a P layer 15, and a collector, layer 14 is segmented. The N layer 19 are provided and connected to the buried layer 12. In the N collector 14, a P base 16 and an N emitter 17 are produced. The surface is covered by an SiO2 film 20, in which an aperture is made. Al electrodes 21, 22, the P layers 15 and a connecting conductor 18 of the N emitter 17 are connected to the N layers 19 and the P base 16. The electrode 23 of the emitter resistance is connected to the main surface of the substrate and the device is completed. The transistor produced by above method has such characteristics that hFE drops rapidly in accordance with large collector current and can provide excellent current limiting function.
摘要翻译：目的：为了确定发射极电阻的任意和大值而不受发射极的组成的限制，通过将发射极和发射极电阻从半导体衬底中取出并组成的方法彼此独立，发射极电阻与衬底。构成：AP +层110和堆叠在层110上的外延层111构成基板11.层111用作发射极电阻，其值以不超过100ohms的值任意确定，由控制电阻率和厚度。设置N埋层12，并在其上堆积外延层13。外延层13由P层15分离，集电体层14被分割。 N +层19设置并连接到掩埋层12.在N个集电极14中，制造P基极16和N发射极17。该表面被形成有孔的SiO 2膜20覆盖。 Al电极21,22，N个发射极17的P层15和连接导体18连接到N +层19和P基极16.发射极电阻的电极23连接到基板和装置完成。通过上述方法制造的晶体管具有如下特征：hFE根据集电极电流迅速下降，并且可以提供优异的限流功能。

67. 发明专利

JPS5721859A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5721859A
公开(公告)日：1982-02-04
申请号：JP9605180
申请日：1980-07-14
申请人： Nec Corp
发明人： UEDA KAZUYOSHI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To obtain high withstand voltage by a semiconductor element of small size by forming an annular additional region around a base region deeper than the base region in a high withstand voltage transistor. CONSTITUTION:A base region 12 and an emitter region 13 are formed in a semiconductor substrate 11 functioning also as a collector, and the same conductive type annular additional region (field rings) 14, 14' as the base region 12 deeper than the base region 12 are formed around the base region 12.
摘要翻译：目的：通过在高耐压晶体管中形成比基极区域更深的基极区域形成环形附加区域，通过小尺寸的半导体元件获得高耐受电压。构成：在也用作集电极的半导体基板11中形成有基极区域12和发射极区域13，并且与基极区域12相比，基极区域12的导电型环状附加区域（场环）14,14' 12形成在基部区域12周围。

68. 发明专利

JP5537996B2 Semiconductor device 有权
公开(公告)号：JP5537996B2
公开(公告)日：2014-07-02
申请号：JP2010046394
申请日：2010-03-03
申请人：株式会社東芝
发明人：渉齋藤 , 昇太郎小野 , 宗久薮崎 , 俊治谷内 , 美穂渡辺
IPC分类号： H01L29/78 , H01L29/06 , H01L29/12 , H01L29/739 , H01L29/861 , H01L29/868
CPC分类号： H01L27/07 , H01L29/72

69. 发明专利

JP2011181805A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011181805A
公开(公告)日：2011-09-15
申请号：JP2010046394
申请日：2010-03-03
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO WATARU , ONO SHOTARO , YABUSAKI MUNEHISA , TANIUCHI SHUNJI , WATANABE YOSHIO
IPC分类号： H01L29/06 , H01L29/12 , H01L29/739 , H01L29/78
CPC分类号： H01L27/07 , H01L29/72
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a short termination length and high reliability. SOLUTION: The semiconductor device has an n + drain layer (first semiconductor region) 2, an (n) drift layer 3 (second semiconductor region) formed on one main surface of the n + drain layer 2, a drain electrode (first main electrode) formed on the other main surface side of the n + drain layer 2 on the side opposite to the one main surface, a (p) base layer (third semiconductor region) 5 selectively formed on the main surface of the (n) drift layer 3 on the side opposite to the n + drain layer, a source electrode (second main electrode) 9 formed to be joined to the (p) base layer 5, and a plurality of buried GR layers 11 (buried semiconductor regions) provided in the (n) drift layer 3 between the drain electrode 1 and source electrode 9 in a terminal region outside an element region where a main current path is formed. The buried GR layers 11 goes away from the main surface of the (n) drift layer 3 where the p-type base layer 5 is formed as the buried GR layers goes outward from the element region. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有短的端接长度和高可靠性的半导体器件。解决方案：半导体器件具有形成在n 漏极层（第一半导体区域）2，（n）漂移层3（第二半导体区域）漏极层2，在与一个主表面相反的一侧形成在n +漏极层相反的一侧的（n）漂移层3的主表面上，源极（第二主电极）形成为与（p）基底层5连接的多个掩埋GR层11（埋入半导体区域），设置在漏电极1和源极电极9之间的（n）漂移层3中的端子区域在形成主电流路径的元件区域外部。埋藏的GR层11随着埋入的GR层从元件区域向外而离开形成p型基底层5的（n）漂移层3的主表面。版权所有（C）2011，JPO＆INPIT

70. 发明专利

JPS61112378A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS61112378A
公开(公告)日：1986-05-30
申请号：JP23315784
申请日：1984-11-07
申请人： Hitachi Ltd
发明人： UEHARA KEIJIRO , KAWAMOTO YOSHIFUMI
IPC分类号： H01L29/73 , H01L21/28 , H01L21/331 , H01L29/72 , H01L29/732
CPC分类号： H01L29/72
摘要： PURPOSE:To obtain a bipolar transistor having a minute emitter width and a long emitter length, by using a fine pattern, which is formed on the periphery of a pattern as an emitter, and forming the emitter and a base contact part by self-alignment without increasing the area of the base. CONSTITUTION:A polycrystalline silicon layer 7 is etched by dry etching technology. Then, the polycrystalline silicon layer 7 can be made to remain only under the eaves of a silicon dioxide film 5. A silicon nitride film 8 is deposited on the entire surface. With this film as a mask, silicon dioxide film 5, 6 and 2 are sequentially etched. Then a structure shown in Figure (e) is obtained. In this structure, a narrow groove part, in which a silicon substrate is exposed, becomes an emitter region. Its width is determined by the thickness of the side-surface oxide film 6 of polycrystalline silicon 4. Therefore accuracy is very high. The polycrystalline silicon 7 is a part, which isolates an emitter and a base contact part. The base contact part is formed in a region, where a central silicon nitride film 3 appears.
摘要翻译：目的：通过使用形成在图案周边的精细图案作为发射极，通过自对准来形成发射极和基极接触部分，获得具有微小发射极宽度和发射极长度的双极晶体管而不增加底座的面积。构成：通过干蚀刻技术蚀刻多晶硅层7。然后，可以使多晶硅层7仅保留在二氧化硅膜5的檐下。在整个表面上沉积氮化硅膜8。以该膜为掩模，依次蚀刻二氧化硅膜5,6和2。然后获得图（e）所示的结构。在该结构中，露出硅衬底的窄槽部成为发射极区域。其宽度由多晶硅4的侧面氧化膜6的厚度决定，因此精度非常高。多晶硅7是隔离发射极和基极接触部分的部分。基部接触部分形成在出现中心氮化硅膜3的区域中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式