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61. 发明专利

JP2009088085A Semiconductor device manufacturing method, semiconductor device manufacturing apparatus, control program, and program storage medium 审中-公开
标题翻译：半导体器件制造方法，半导体器件制造设备，控制程序和程序存储介质
公开(公告)号：JP2009088085A
公开(公告)日：2009-04-23
申请号：JP2007253410
申请日：2007-09-28
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： HATTA KOICHI , NISHIMURA EIICHI
IPC分类号： H01L21/3065 , H01L21/768 , H01L23/522
CPC分类号： H01L21/32139 , H01L21/0337
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method that achieves further process simplification and further reduction in manufacturing cost, as compared with the conventional one, while achieving improvement in productivity, and to provide a semiconductor device manufacturing apparatus, a control program, and a program storage medium.
SOLUTION: The semiconductor device manufacturing method includes a film-forming step for forming an SiO
2 film 105 on a pattern of an organic film 102, an etching step for etching so as to allow the SiO
2 film 105 to remain only on the sidewall part of the pattern of the organic film 102, and a step for forming a pattern of the SiO
2 film 105 by removing the pattern of the organic film 102.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件制造方法，其与现有技术相比，在实现生产率提高的同时实现进一步的工艺简化和进一步降低制造成本，并且提供半导体器件制造装置，控制程序和程序存储介质。解决方案：半导体器件制造方法包括在有机膜102的图案上形成SiO 2 SB薄膜105的成膜步骤，用于蚀刻的蚀刻步骤，以使SiO 2 薄膜105仅保留在有机薄膜102的图案的侧壁部分上，以及通过去除图案来形成SiO 2 SB薄膜105的图案的步骤的有机膜102.版权所有（C）2009，JPO＆INPIT

62. 发明专利

JP2008177493A Substrate processing apparatus and focus ring 有权
标题翻译：基板加工设备和聚焦环
公开(公告)号：JP2008177493A
公开(公告)日：2008-07-31
申请号：JP2007011706
申请日：2007-01-22
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： MIYAGAWA MASAAKI , NISHIMURA EIICHI
IPC分类号： H01L21/3065 , C23F4/00 , H01L21/683
CPC分类号： H01J37/32642 , H01J37/32623
摘要： PROBLEM TO BE SOLVED: To provide a substrate processing apparatus which can fully improve heat transmission efficiency between a focus ring and a placing table. SOLUTION: A substrate processing apparatus 10 has a chamber 11 for housing a wafer W, a susceptor 12 disposed inside the chamber 11, an electrostatic chuck 22 which is disposed in an upper part of the susceptor 12 for placing the wafer W and a focus ring 24 placed on the electrostatic chuck 22 to enclose a circumferential edge of the placed wafer W. A heat transmission film 39 formed of resin by print processing is formed in a contact surface 24a to the electrostatic chuck 22 in the focus ring 24. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够充分提高聚焦环和放置台之间的热传递效率的基板处理装置。解决方案：基板处理装置10具有用于容纳晶片W的室11，设置在室11内部的基座12，设置在基座12的上部以放置晶片W的静电卡盘22和放置在静电卡盘22上的聚焦环24包围放置的晶片W的周缘。通过印刷处理由树脂形成的传热膜39形成在与聚焦环24中的静电卡盘22的接触表面24a中。版权所有（C）2008，JPO＆INPIT

63. 发明专利

JP2008135632A Method and system for manufacturing capacitor electrode, and recording medium 有权
标题翻译：用于制造电容器电极的方法和系统以及记录介质
公开(公告)号：JP2008135632A
公开(公告)日：2008-06-12
申请号：JP2006321680
申请日：2006-11-29
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI
IPC分类号： H01L21/8242 , H01L21/302 , H01L27/108
CPC分类号： H01L21/31116 , H01L21/67069 , H01L28/91
摘要： PROBLEM TO BE SOLVED: To remove an object to be processed, such as an film, exposing on the surface of a substrate, without causing problems, such as, a leaning generated. SOLUTION: A method for manufacturing a capacitor electrode 103, by removing a silicon oxide film 100 on the surface of the substrate W, comprises a step of transforming the silicon oxide film 100 into a residue product by making the temperature of the substrate W at a first processing temperature; supplying a gas containing halogenic element, and chemically reacting the silicon oxide film 100 with the halogen element; and a step of removing the silicon oxide film 100 transformed to the reaction product, by setting the temperature of the substrate W, to a second processing temperature higher than the first processing temperature. The present invention can avoid the "leaning" at the removing of the silicon oxide film 100, left in the periphery of the capacitor electrode 103, after the cylindrical capacitor electrode 103 is formed on the inner surface of a storage node hole 101. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：除去诸如膜的被处理物体，在基板的表面上暴露，而不会产生诸如倾斜的问题。解决方案：通过去除衬底W的表面上的氧化硅膜100来制造电容器电极103的方法包括通过使衬底的温度将氧化硅膜100转化成残余物的步骤 W处于第一处理温度; 供给含有卤元素的气体，并使氧化硅膜100与卤素元素化学反应; 以及通过将基板W的温度设定为高于第一处理温度的第二处理温度来除去转化为反应产物的氧化硅膜100的工序。本发明可以避免在将圆筒形电容器电极103形成在存储节点孔101的内表面上之后，留下在电容器电极103周围的氧化硅膜100的“倾斜”。
版权所有（C）2008，JPO＆INPIT

64. 发明专利

JP2008010662A Substrate processing method and substrate processing apparatus 有权
标题翻译：基板加工方法和基板加工装置
公开(公告)号：JP2008010662A
公开(公告)日：2008-01-17
申请号：JP2006180185
申请日：2006-06-29
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI
IPC分类号： H01L21/304 , B08B3/00 , B08B3/10 , G02F1/13 , G02F1/1333 , H01L21/28 , H01L21/302 , H01L21/3205
摘要： PROBLEM TO BE SOLVED: To provide a substrate processing method capable of easily removing a remaining product due to a hydrofluoric acid.
SOLUTION: An HF gas is supplied to a wafer W having a thermal oxidation film 61 and a BPSG film 63 to selectively etch the BPSG film 63. Subsequently, an NH
3 gas is supplied to the wafer W, and allows an H
2 SiF
6 gas to react to an NH
3 gas of the remaining product 64 generated on the basis of the reaction between the SiO
2 and the hydrofluoric acid to generate NH
4 F and SiF
4 . Further, the NH
4 F is allowed to sublimate.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够容易地除去由氢氟酸引起的剩余产物的基板处理方法。解决方案：将HF气体供给到具有热氧化膜61和BPSG膜63的晶片W上，以选择性地蚀刻BPSG膜63.随后，将NH 3 SB 3气体供应到晶片W，并且允许H SB SB 6气体与基于所述晶片W产生的剩余产物64的NH 3 SB 3气体反应。 SiO 2 SBB与氢氟酸之间的反应，以产生NH 3 SB 4和SBF 4。此外，允许NH 4 SBF升华。版权所有（C）2008，JPO＆INPIT

65. 发明专利

JP2007266455A Substrate processing apparatus and method, and storage medium 审中-公开
标题翻译：基板加工设备和方法以及存储介质
公开(公告)号：JP2007266455A
公开(公告)日：2007-10-11
申请号：JP2006091635
申请日：2006-03-29
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI
IPC分类号： H01L21/302
CPC分类号： H01L21/31111 , H01L21/67069
摘要： PROBLEM TO BE SOLVED: To provide a substrate processing apparatus capable of increasing the degree of freedom of arrangement and efficiently removing an oxide layer. SOLUTION: The second process unit 34 of a second process ship 12 comprises: a chamber 38 for housing a wafer W for which a deposit film 126 with an SiO 2 layer 123 is formed, an ESC 39 arranged inside the chamber 38 for mounting the wafer W, a heater 103 of a shower head 40 arranged so as to face the ESC 39, a plurality of pusher pins 56 which can be freely projected from the upper surface of the ESC 39, an ammonia gas supply system 105 for supplying ammonia gas into the chamber 38, and a hydrofluoric gas supply system 127 for supplying hydrofluoric gas into the chamber 38. The pusher pins 56 move the wafer W for which a product is generated on a surface from the SiO 2 layer 123, the ammonia gas and the hydrofluoric gas to the vicinity of the heater 103. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够提高排列自由度并有效去除氧化物层的基板处理装置。解决方案：第二处理船12的第二处理单元34包括：用于容纳晶片W的室38，其中形成有具有SiO 2 层123的沉积膜126，ESC 39设置在室38内部，用于安装晶片W，喷淋头40的加热器103布置成面向ESC 39，多个推动销56可以从ESC 39的上表面自由地突出，用于向室38供给氨气的氨气供给系统105以及用于向室38供给氢氟酸气体的氢氟气供给系统127.推杆56将表面产生产物的晶圆W从SiO 层123，氨气和氢氟酸气体到加热器103附近。版权所有（C）2008，JPO＆INPIT

66. 发明专利

JP2006270032A Surface treatment method for substrate, cleaning method for substrate and program 有权
标题翻译：基板表面处理方法，基板和程序清洁方法
公开(公告)号：JP2006270032A
公开(公告)日：2006-10-05
申请号：JP2005278844
申请日：2005-09-26
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI , ORII TAKEHIKO
IPC分类号： H01L21/304 , H01L21/027
CPC分类号： H01L21/02063 , G03F7/42 , H01L21/02054 , H01L21/6719 , H01L21/67196 , H01L21/67201
摘要： PROBLEM TO BE SOLVED: To provide a surface treatment method for a substrate by which adherent materials of the substrate are removed to obtain a clean substrate. SOLUTION: A contact hole 303 for source-drain contact is formed in an insulating film 301 formed on the surface of the wafer W by using a resist film 302. In the wafer W, SPM cleaning is performed for removing the resist film, then SC1 cleaning is performed for removing particles 304, then SC2 cleaning is performed for removing metal contamination 305, then DHF cleaning is performed for removing a natural oxide film generated on the surface of the wafer W, and then spin drying is performed. Then the wafer W is exposed to a mixed gas of an ammonia and hydrofluoric gas under a specified pressure, and a product having a complex structure which is quality-changed from SiO 2 for forming a water mark 307 is heated up to a specified temperature. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于去除衬底的粘附材料以获得清洁衬底的衬底的表面处理方法。解决方案：通过使用抗蚀剂膜302在形成在晶片W的表面上的绝缘膜301中形成用于源极 - 漏极接触的接触孔303.在晶片W中，执行SPM清洁以除去抗蚀剂膜，则进行SC1清洗以除去颗粒304，然后执行SC2清洁以除去金属污染物305，然后执行DHF清洁以除去在晶片W的表面上产生的自然氧化膜，然后进行旋转干燥。然后将晶片W在特定压力下暴露于氨和氢氟酸气体的混合气体中，形成水痕307的由SiO 2 质量变化的复合结构的产物是加热至指定温度。版权所有（C）2007，JPO＆INPIT

67. 发明专利

JP2006253633A Processing method of substrate, cleaning method after chemical mechanical polishing, process for fabricating electronic device and program 有权
标题翻译：基板处理方法，化学机械抛光后的清洗方法，电子设备和程序的制作工艺
公开(公告)号：JP2006253633A
公开(公告)日：2006-09-21
申请号：JP2005278841
申请日：2005-09-26
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI , IWASAKI KENYA
IPC分类号： H01L21/304
CPC分类号： H01L21/31116 , H01L21/02063 , H01L21/02074 , H01L21/31056
摘要： PROBLEM TO BE SOLVED: To provide a process for fabricating an electronic device in which control of removing quantity of a damaged layer or shaving remnant on the surface of an insulating film can be carried out easily. SOLUTION: A low permittivity interlayer insulating film 115 is deposited to cover an insulating film 113 on a wafer W where a wiring 114 is formed (B), a via hole 118 is bored in the low permittivity interlayer insulating film 115 (C), a conductive film 121 of copper is deposited on the low permittivity interlayer insulating film 115 and the via hole 118 is filled with copper (F), the low permittivity interlayer insulating film 115 is exposed by polishing the conductive film 121 by CMP (G), the low permittivity interlayer insulating film 115 having shaving remnants 116, reaction products 117, residue and false SiO 2 layer 124 on the surface is exposed to the atmosphere of mixture gas of ammonia gas and hydrogen fluoride gas (H), and a product layer 123 deteriorated from the false SiO 2 layer 124 is heated at a predetermined temperature (I). COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造电子装置的方法，其中可以容易地进行控制绝缘膜表面上的损伤层或剃刮残留物的去除量。解决方案：沉积低介电常数层间绝缘膜115以覆盖形成布线114的晶片W上的绝缘膜113（B），在低介电常数层间绝缘膜115（C ），在低介电常数层间绝缘膜115上沉积铜的导电膜121，并且通孔118填充有铜（F），通过CMP（G）对导电膜121进行抛光来使低介电常数层间绝缘膜115曝光），表面上具有剃刮残留物116，反应产物117，残留物和假SiO 2 SB 2层124的低介电常数层间绝缘膜115暴露于氨气和氟化氢气体的混合气体的气氛（H），并且从假SiO 2 SB 12层124劣化的产物层123在预定温度（I）下被加热。版权所有（C）2006，JPO＆NCIPI

68. 发明专利

JP2005243681A Film modifying method, film modifying apparatus and control method of amount of slimming 审中-公开
标题翻译：电影修改方法，胶片修改装置及滑动量控制方法
公开(公告)号：JP2005243681A
公开(公告)日：2005-09-08
申请号：JP2004047611
申请日：2004-02-24
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI , TANAKA TAKASHI , YO HAJIME , HONDA MINORU , IWASHITA MITSUAKI
IPC分类号： G03F7/40 , A61N5/00 , G03C5/00 , G21G5/00 , H01L21/027
CPC分类号： G03F7/40
摘要： PROBLEM TO BE SOLVED: To provide a film modifying method which can transfer an original resist pattern to a film layer etched correctly as much as possible by suppressing the contraction of a photoresist film layer, even if the irradiation of an electron beam performs the hardening process of the photoresist film layer, and which, as a result, does not have a risk of the occurrence of a failure in a circuit, and a film modifying apparatus, and to provide a control method of the amount of slimming by the irradiation of an electron beam collectively.
SOLUTION: This film modifying method includes a step of irradiating the electron beam B in a state that a photoresist film layer 2 is cooled when the electron beam B is irradiated to the photoresist film layer 2 to modify the photoresist film layer 2.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：为了提供一种膜修饰方法，其可以通过抑制光致抗蚀剂膜层的收缩将原始抗蚀剂图案转印到尽可能多地蚀刻的膜层上，即使电子束的照射执行光致抗蚀剂膜层的硬化处理，其结果不具有电路发生故障的风险，以及膜修改装置，并且提供通过所述光致抗蚀剂膜层的减肥量的控制方法一起照射电子束。解决方案：该膜修饰方法包括在电子束B照射到光致抗蚀剂膜层2上时光致抗蚀剂膜层2被冷却的状态下照射电子束B以修饰光致抗蚀剂膜层2的步骤。版权所有（C）2005，JPO＆NCIPI

69. 发明专利

JP2014209514A パターンを形成する方法有权
标题翻译：形成图案的方法
公开(公告)号：JP2014209514A
公开(公告)日：2014-11-06
申请号：JP2013085940
申请日：2013-04-16
申请人：東京エレクトロン株式会社 , Tokyo Electron Ltd
发明人： MORIKITA SHINYA , NISHIMURA EIICHI , YAMASHITA FUMIKO
IPC分类号： H01L21/3065 , H01L21/027
CPC分类号： H01L21/31133 , B81C1/00031 , B81C2201/0149 , G03F7/0002 , H01J37/32091 , H01J37/32577 , H01L21/02118 , H01L21/02351 , H01L21/0271 , H01L21/31138 , H01L21/31144
摘要：【課題】ブロック共重体の相分離した一方の領域のみを削除してパターンを形成する方法の提供。【解決手段】a)下地層上に第1のポリマー及び第2のポリマーを含む自己組織化可能なブロック共重合体層を形成する工程(ST1)と、(b)ブロック共重合体層に第1のポリマーを含む第1の領域及び第2のポリマーを含む第2の領域を形成するよう被処理体を処理する工程(ST2)と、(c)被処理体を処理する工程の後、容量結合型のプラズマ処理装置内において第2の領域の膜厚の途中まで該第2の領域をエッチングする工程(ST3)と、(d)第2の領域をエッチングする工程の後、プラズマ処理装置の上部電極に負の直流電圧を印加して該上部電極から二次電子を発生させ、該二次電子を被処理体に照射する工程(ST4)と、(e)二次電子を被処理体に照射する工程の後、プラズマ処理装置内において第2の領域を更にエッチングする工程(ST5)と、を含む。【選択図】図1
摘要翻译：要解决的问题：提供通过仅删除嵌段共聚物的相分离区域的一个区域形成图案的方法。解决方案：形成图案的方法包括以下步骤：a）形成自组织嵌段共聚物层（ST1）上包含第一和第二聚合物的层; （b）加工工件，使得包含第一聚合物的第一区域和包括第二聚合物的第二区域形成在嵌段共聚物层中（ST2）; （c）在所述工件加工步骤（ST3）之后，在电容耦合等离子体处理装置中将所述第二区域蚀刻到所述第二区域的膜厚度的中间; （d）通过向上电极施加负的直流电压并在第二区域蚀刻步骤（ST4）之后用二次电子照射工件，从等离子体处理装置的上部电极产生二次电子; 和（e）在工件照射步骤之后进一步蚀刻等离子体处理装置中的第二区域（ST5）。

70. 发明专利

JP2014103155A Plasma processing method and plasma processing device 有权
标题翻译：等离子体处理方法和等离子体处理装置
公开(公告)号：JP2014103155A
公开(公告)日：2014-06-05
申请号：JP2012252385
申请日：2012-11-16
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI , SHOSHI TADASHI , SONE TAKASHI
IPC分类号： H01L21/3065 , H01L21/8246 , H01L27/105 , H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , H01J37/32449 , H01J37/32724
摘要： PROBLEM TO BE SOLVED: To provide a plasma processing method and a plasma processing device, capable of improving MRAM element characteristics by preventing leak current.SOLUTION: A plasma processing method etches a multilayer film material using a plasma processing device. The plasma processing device comprises a processing container and a gas supply unit. The multilayer film material includes a laminate structure in which a first magnetic layer, an insulating layer, a second magnetic layer, and a mask material are laminated in this order. The plasma processing method includes a mask forming step and an etching step. The mask forming step forms a mask on the second magnetic layer by etching the mask material. The etching step supplies a process gas to the processing container, generates plasma, etches the second magnetic layer using the mask, and terminates etching on a surface of the insulating layer. The second magnetic layer includes CoFeB. The insulating layer includes MgO. The process gas includes Hand F or a fluorine compound.
摘要翻译：要解决的问题：提供能够通过防止泄漏电流来提高MRAM元件特性的等离子体处理方法和等离子体处理装置。解决方案：等离子体处理方法使用等离子体处理装置蚀刻多层膜材料。等离子体处理装置包括处理容器和气体供应单元。多层膜材料包括依次层叠第一磁性层，绝缘层，第二磁性层和掩模材料的叠层结构。等离子体处理方法包括掩模形成步骤和蚀刻步骤。掩模形成步骤通过蚀刻掩模材料在第二磁性层上形成掩模。蚀刻步骤向处理容器提供处理气体，产生等离子体，使用掩模蚀刻第二磁性层，并终止在绝缘层的表面上的蚀刻。第二磁性层包括CoFeB。绝缘层包括MgO。工艺气体包括手F或氟化合物。

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