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61. 发明专利

JPS61281710A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS61281710A
公开(公告)日：1986-12-12
申请号：JP12274485
申请日：1985-06-07
申请人： NIPPON TELEGRAPH & TELEPHONE , NEC CORP
发明人： WAKIMOTO TSUTOMU , AKAZAWA YUKIO , ISHIHARA NOBORU , NAKAJIMA MASAHIKO
IPC分类号： H03F1/02 , H03F1/42 , H03F3/45
摘要： PURPOSE:To increase the variable range of a peaking capacitor by using a mirror capacitance of a transistor (TR) in addition to a diffusion capacitance as a peaking capacitance of an amplifier circuit having a peaking function. CONSTITUTION:An input TR 6, a load resistor 7 and a series resistor 8 form a series feedback type amplifier circuit. The 1st TR 18, a capacitor 20 and a resistor 21 are used to use a mirror capacitance of the TR 18 and the diffusion capacitance between the base and emitter as a peaking capacitance and the mirror capacitance of the TR 18 and the capacitance between the base and emitter act like the peaking capacitance. It is possible to change the peaking capacitance by changing the current Ip flowing to the TR 18. Thus, an optional peaking characteristic is obtained by setting optionally the voltage impressed to a peaking control terminal 23 so as to stabilize the broad band setting of the amplifier.

62. 发明专利

JPS60111508A INPUT MATCHING CIRCUIT 失效
公开(公告)号：JPS60111508A
公开(公告)日：1985-06-18
申请号：JP22028083
申请日：1983-11-21
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： AKAZAWA YUKIO , ISHIHARA NOBORU , OBARA MAMORU
IPC分类号： H03F3/343 , H03F3/34 , H03K19/018
摘要： PURPOSE:To realize a high band characteristic by using a two-terminal power supply circuit where its AC impedance is decreased less than its DC impedance so as to attain direct coupling at low power consumption and add a capacitor thereto. CONSTITUTION:An emitter of a bipolar NPN transistor (TR)Q31 is connected to a power terminal 4 at a low potential, a base is connected to one terminal of resistors R32, R34, and the terminal 4 is connected to the other terminal of the R33. Furthermore, the other terminal of the R32 and the collector of the TRQ31 are connected to one terminal of the resistor R31 and a capacitor C31 respectively. The other terminal of the R31, C31 is connected to a power terminal 3 at high potential and a signal input terminal 1 and a signal output terminal 2 are used as the collector terminal of the TRQ31. Thus, the terminal 2 is used as the collector terminal of the TRQ31. Since the part consisting of the R32, R33 and the TRQ31 is a so-called 2-terminal constant voltage circuit and a current starts flowing at a voltage being the operating start voltage or over, the DC resistance at the operating point is increased more than the AC resistance.

63. 发明专利

JPS5943024B2 JPS5943024B2 - 失效
公开(公告)号：JPS5943024B2
公开(公告)日：1984-10-19
申请号：JP5967479
申请日：1979-05-17
申请人： Nippon Telegraph & Telephone
发明人： NISHINO YUTAKA , AKAZAWA YUKIO , SUDO TSUNETAKA , ITO MITSUTOSHI
IPC分类号： H04M1/76 , H03B1/00 , H04M1/50 , H04M19/04
CPC分类号： H04M1/50

64. 发明专利

JPS5810920A DIGITAL-TO-ANALOG CONVERTER 失效
公开(公告)号：JPS5810920A
公开(公告)日：1983-01-21
申请号：JP10813781
申请日：1981-07-13
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MATSUTANI YASUYUKI , AKAZAWA YUKIO , IWATA ATSUSHI
IPC分类号： H03M1/10 , H03M1/00 , H03K13/02
摘要： PURPOSE:To obtain high speed, by instantly determining a switching point from a digital signal of a part of an input code. CONSTITUTION:When a digital input code is applied to a terminal 1, a signal of high-order (m+1) bits is applied to a switching point generating circuit 4, the area is designated and when a switching point is present in the area, a signal of the low-order (n-m-1) bits is outputted, and when no switching point is present, O is outputted. A digital comparator 3 compares the code data in the low- order (n-m-1) bits in the digital input signal with an output from the circuit 4, and when the input code data is greater, a carry signal is outputted. The shift amount to be corrected corrsponding to each input code is obtained from a code shift amount generating circuit 5. The shift amount and the input code are summed with a digital adder 6, the summed output is applied to the original DC, from which an analog output corresponding to the input code is obtained.

65. 发明专利

JPS55151839A AUTOMATIC LEVEL CONTROL CIRCUIT FOR TELEPHONE 失效
公开(公告)号：JPS55151839A
公开(公告)日：1980-11-26
申请号：JP5909979
申请日：1979-05-16
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NISHINO YUTAKA , YOSHIRI MAKOTO , AKAZAWA YUKIO , NISHIHARA KANEYUKI
IPC分类号： H04M1/76 , H03G3/00 , H04M1/50
摘要： PURPOSE:To reduce the change of the dial DC level by giving the control to the bias state of the amplifying circuit forming the output circuit of the dial generator and thus controlling the DC power consumption of the amplifying circuit, thus preventing the malfunction of the exchange. CONSTITUTION:Control part 5 of the automatic level control circuit detects the current supplied from the station, and then generates the binary signal. Controlled part 6 receive the control signal from part 5 through control signal line 8. And in case the control is given to the AC level of the dial signal, the control is also given concurrently to the bias state of amplifying circuit 3 forming the output circuit of dial generator 2. Thus the DC power consumption is controlled for circuit 3 to eliminate the change of the dial DC level. As a result, the malfunction can be avoided for the exchange.

66. 发明专利

JPS55124330A FLIPPFLOP CAPABLE OF COUNTING AND INITIAL SETTING 失效
公开(公告)号：JPS55124330A
公开(公告)日：1980-09-25
申请号：JP3193379
申请日：1979-03-19
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： AKAZAWA YUKIO , SUDOU TSUNETAKA , MURATA MASANORI , ITOU MITSUTOSHI
IPC分类号： H03K21/38 , H03K3/037 , H03K23/00
摘要： PURPOSE:To simplify the circuit constitution as well as realize both the miniaturization and the low power consumption, by forming the additional circuit of the initial value setting function with the FF circuit and the logic gate which is capable of the high-speed action for the initial value setting. CONSTITUTION:Initial setting input terminal 15 and counting-initial setting switch terminal 11 are connected to the input ends of the 1st and the 2nd NAND gates 31 and 32. And the output of gates 31 and 32 are supplied to the 3rd NAND gate 33. Furthermore, the output of gate 31 is supplied to the 4th NAND gate 34, and the output of gates 32 and 34 are supplied to NAND gate 35. The output of gate 33 is applied to reset terminal R of FF circuit 18; the output of gate 35 is applied to set terminal S of circuit 18; and the clock pulse sent from clock terminal 21 is applied to trigger terminal T. Then the number of the gates is reduced for the range during which signal R applied to terminal 11 reaches reset terminal R, and thus the speed of the initial value setting action is increased. And the counting speed is decided according to the velocity performance of circuit 18. In this way, the circuit constitution can be simplified.

67. 发明专利

JPH11220329A VOLTAGE CONTROLLED OSCILLATOR 失效
公开(公告)号：JPH11220329A
公开(公告)日：1999-08-10
申请号：JP3677498
申请日：1998-02-02
申请人： NIPPON TELEGRAPH & TELEPHONE , NIHON DEMPA KOGYO CO
发明人： KUBO KUICHI , FUJIMORI YOSHIMITSU , ONO KOZO , NAKAMURA MAKOTO , ISHIHARA NOBORU , AKAZAWA YUKIO
IPC分类号： H03B5/32 , H03B5/12
摘要： PROBLEM TO BE SOLVED: To provide a voltage controlled oscillator which uses a voltage variable capacity element applying a MOS(metal oxide semiconductor) that has a large capacity change when the voltage is set of a low level. SOLUTION: A voltage controlled oscillator which varies the oscillation frequency of an oscillation circuit 2 by a voltage variable capacity element uses a MOS element 4 whose gate-source electrostatic capacity varies in steps based on the threshold voltage against the DC voltage that is applied between a gate and a source. Then the sine wave-shaped oscillation voltage generated by the circuit 2 and the DC voltage are applied between the gate and the source. Thus, an operating area Δθ (rad) which exceeds the threshold voltage of a single cycle of the oscillation voltage is controlled by the DC voltage. At the same time, the distortion oscillation current that is generated between the gate and the source with the area Δθ defined as its passing area is also controlled to vary the basic wave component of the distortion oscillation current to the oscillation voltage. As a result, the substantial gate-source capacity is varied to the basic wave component.

68. 发明专利

JPH10132658A PHOTOELECTRIC TRANSDUCING CIRCUIT 失效
公开(公告)号：JPH10132658A
公开(公告)日：1998-05-22
申请号：JP30240196
申请日：1996-10-29
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HIROSE MASAKI , KISHINE YOSHIMICHI , ISHIHARA NOBORU , AKAZAWA YUKIO
IPC分类号： G01J1/44
摘要： PROBLEM TO BE SOLVED: To suppress the effect of parasitic component of a photoelectric transducing element by inserting a damping resistor between a conversion resistor and the photoelectric transducing element. SOLUTION: A DC bias power supply 11 is applied to the cathode terminal K of a photoelectric transducing element module 10 having anode terminal A connected with one end of a damping resistor RD and a current/voltage conversion resistor RT is connected between the other end of the damping resistor RD and the earth. A DC cut capacitor CC is connected with the common joint of the conversion resistor RT and the anode terminal A. A current derived from a current source iPD depending on the intensity of a received optical signal passes from the anode A through the damping resistor RD and then converted into a voltage signal through the conversion resistor RT. Steep peaking is suppressed in the characteristic frequency region through insertion of the damping resistor RD and a good waveform can be outputted. Furthermore, effect of parasitic impedance is suppressed through optimization of the characteristic impedance of a transmission line and a wide band characteristics can be achieved.

69. 发明专利

JPH1079628A OUTPUT BUFFER CIRCUIT 失效
公开(公告)号：JPH1079628A
公开(公告)日：1998-03-24
申请号：JP25397096
申请日：1996-09-05
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KISHINE KEIJI , HIROSE MASAKI , ISHIHARA NOBORU , AKAZAWA YUKIO
IPC分类号： H03K19/0175 , H03F3/45 , H03F3/68
摘要： PROBLEM TO BE SOLVED: To realize an output buffer circuit in which a linear amplification range is extended without deteriorating gain and power consumption. SOLUTION: This circuit is provided with a 1st linear amplifier 1 and a 2nd linear amplifier 2. The 2nd linear amplifier 2 is composed of a differential amplifier provided with differential pair transistors(TRs) Q1, Q2 and one terminal of resistors R3, R4 is connected to emitters of the TRs Q1, Q2 and the other terminal of the resistors R3, R4 is connected in common to a current source SC1.

70. 发明专利

JPH1065473A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH1065473A
公开(公告)日：1998-03-06
申请号：JP22081996
申请日：1996-08-22
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SATO TSUTOMU , SHIMIZU KAZUYOSHI , YOITA MASAYUKI , AKAZAWA YUKIO , ISHIHARA NOBORU , NAKAMURA MAKOTO
IPC分类号： H03G11/00 , H03F1/30 , H03F3/34 , H03F3/45
摘要： PROBLEM TO BE SOLVED: To provide the amplifier circuit operated stably independently of the dispersion in the manufacture process, temperature, power supply fluctuation and presence of noise with respect to the amplifier circuit. SOLUTION: The amplifier circuit provided with an automatic threshold level setting circuit 10 that detects and holds a peak value Vp and a bottom value Vb of a burst signal Vi to generate an intermediate threshold level Vth and an amplitude limit amplifier circuit 20 amplifying the input signal Vi in a linear region around the threshold level Vth is provided with an offset compensation circuit 30 that applies feedback to the circuit 20 so as to obtain a prescribed level for the signal level based on an output signal V0 at non-signal so as to compensate a detection error in the threshold level Vth and other input offset component, and also with a comparator circuit 51 compares the detected peak level Vp or bottom level Vb with a prescribed reference level and with a clamp circuit T55 which clamps the output signal V0 to a prescribed level according to the comparison output and clamps the output signal V0 to a desired level when no burst is received.

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