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61. 发明专利

JPS5135266A 失效
公开(公告)号：JPS5135266A
公开(公告)日：1976-03-25
申请号：JP10781474
申请日：1974-09-20
申请人： HITACHI LTD
发明人： YAMASHITA KIICHI , TAKASAKI YOSHITAKA
IPC分类号： H03M5/12 , H04L25/49

62. 发明专利

JPH0630429B2 失效
公开(公告)号：JPH0630429B2
公开(公告)日：1994-04-20
申请号：JP24955584
申请日：1984-11-28
申请人： HITACHI LTD
发明人： TAKYASU YOSHIHIRO , YAMASHITA KIICHI , SASAKI SHINYA , TAKASAKI YOSHITAKA
IPC分类号： H03G11/02 , H03G11/00

63. 发明专利

JPH0698324A PICTURE INFORMATION TRANSMISSION SYSTEM 失效
公开(公告)号：JPH0698324A
公开(公告)日：1994-04-08
申请号：JP24617492
申请日：1992-09-16
申请人： HITACHI LTD
发明人： TAKASAKI YOSHITAKA
IPC分类号： H04N7/015 , H04N7/01 , H04N21/2343 , H04N21/239 , H04N21/41 , H04N21/431 , H04N21/4728 , H04N7/173 , H04N7/00
摘要： PURPOSE:To improve the performance of high definition by displaying a picture with small sized patterns being divisions of the picture. CONSTITUTION:Partial display and entire display 55 are implemented on separate screens simultaneously. Optional four divided patterns 36 are selectively displayed on four partial pattern use display devices 36-1-36-4 arranged side by side. In the case of Figure (b), 6 partial pattern use display devices 36-1-36-6 are employed. The quantity of information is reduced by applying rough scanning to an entire pattern indication and displaying partially the pattern on separate screens as to detailed indication thereby reducing the transmission capacity and the cost of the display devices. As to the divided pattern indication for the detailed portion, since the displayed part is selected by a receiver subscriber, the required detailed pattern information is optionally selected from the entire pattern. Furthermore, since existing display devices are employed, the compatibility with an existing system is excellent and the system is extended flexibly.

64. 发明专利

JPH0686232A IMAGE INFORMATION TRANSMISSION SYSTEM 失效
公开(公告)号：JPH0686232A
公开(公告)日：1994-03-25
申请号：JP23615392
申请日：1992-09-03
申请人： HITACHI LTD
发明人： TAKASAKI YOSHITAKA
IPC分类号： H04N7/015 , H04N7/00
摘要： PURPOSE:To decide the display method of a window screen by the selection of a user in a system sharing a part of a display with the reception display of another screen information(window screen). CONSTITUTION:Buffer memory 81 is provided at a store and switching means 60, and the reception information of the window screen is outputted as it is or it is stored in the buffer memory 81 transiently by a switching circuit 63. Such switching depends on the selection of the user. For example, when direct display is performed and the masking time of a master screen exceeds limitation, received window screen information is housed once, and re-display can be performed appropriately. In such a way, since the display method of the window screen can be decided by the selection of the user, flexibility on a system operation can be increased.

65. 发明专利

JPH0685809A DIGITAL TRANSMISSION MULTIPLEXING SYSTEM 失效
公开(公告)号：JPH0685809A
公开(公告)日：1994-03-25
申请号：JP23686992
申请日：1992-09-04
申请人： HITACHI LTD
发明人： TAKASAKI YOSHITAKA
IPC分类号： H04J3/00 , H04L5/00 , H04L7/08
摘要： PURPOSE:To simplify the frame processing circuit and to reduce power consumption by interleaving a frame signal with an information signal so as to eliminate the need for signal processing such as time compression expansion and speed conversion. CONSTITUTION:A frame signal in a pulse train (a) inputted from an input terminal 1 is extracted by using a sampling clock (c) resulting from a clock signal (b) subject to 1/2 frequency division at a logical gate 2 and inputted to a shift register 5. An AND circuit 6 detects a block pattern 10X10 from an output of tire shift register 5, the pattern is delayed by one-bit at a delay line 7 and the result is inputted to an OR circuit 8, its output is given to an AND circuit 11, which inhibits the block clock (d). The AND circuit 11 outputs logical 1 when out of synchronism is caused between the block clock (d) and a head of the block to shift a clock counter 10 by one bit. The delay line 7 is used to prevent the counter 10 from being shifted due to a code error. An AND gate 3 applies 1-bit shift sampling to the sampling clock (c) to extract an information signal pulse train.

66. 发明专利

JPH0645873A VARIABLE EQUALIZER 失效
公开(公告)号：JPH0645873A
公开(公告)日：1994-02-18
申请号：JP10641793
申请日：1993-05-07
申请人： HITACHI LTD
发明人： YUMOTO OSAMU , SUZUKI TOSHIRO , TAKATORI HIROSHI , TAKASAKI YOSHITAKA
IPC分类号： H03H19/00 , H03H15/00 , H03H17/00 , H03H21/00 , H04B3/14
摘要： PURPOSE:To provide a variable waveform equalizer provided in a repeater circuit or a receiver used without sacrificing the equalization precision at the time of long distance transmission of a digital signal. CONSTITUTION:This equalizer consists of a first unit variable equalizer 3 whose variable range is stepwise changed, a second unit variable equalizer 4 which is connected in series to the first unit variable equalizer 3 and has the variable unit stepwise changed and has the variable step width of the first unit variable equalizer 3 as a maximum equalization width and has plural kinds of variable step width within the maximum equalization width, means 5, 6, and 7 which compare the output signal of the second unit variable equalizer 4 with reference signals, and a control means 8 which converts comparison outputs to a digital signal and uses plural upper bits of this digital signal to control the first unit variable equalizer 3 and uses plural lower bits to control the second unit variable equalizer 4.

67. 发明专利

JPH0531335B2 失效
公开(公告)号：JPH0531335B2
公开(公告)日：1993-05-12
申请号：JP1622882
申请日：1982-02-05
申请人： HITACHI LTD
发明人： TAKAHASHI YASUSHI , NAGANO KATSUYUKI , TAKASAKI YOSHITAKA
IPC分类号： H04L7/033 , H04L7/027

68. 发明专利

JPH054866B2 失效
公开(公告)号：JPH054866B2
公开(公告)日：1993-01-21
申请号：JP17322082
申请日：1982-10-04
申请人： HITACHI LTD
发明人： TAKASAKI YOSHITAKA , TAKAHASHI YASUSHI
IPC分类号： H03M5/12 , H04L25/05 , H04L25/38 , H04L25/49

69. 发明专利

JPH0212063B2 失效
公开(公告)号：JPH0212063B2
公开(公告)日：1990-03-16
申请号：JP4477385
申请日：1985-03-08
申请人： HITACHI LTD
发明人： SUZUKI TOSHIRO , TAKATORI HIROSHI , YUMOTO OSAMU , TAKASAKI YOSHITAKA
IPC分类号： H04B3/06 , H04L25/03

70. 发明专利

JPH01154642A FRAME SYNCHRONIZING DEVICE 失效
公开(公告)号：JPH01154642A
公开(公告)日：1989-06-16
申请号：JP31190587
申请日：1987-12-11
申请人： HITACHI LTD
发明人： TAKASE MASAHIKO , TAKASAKI YOSHITAKA
IPC分类号： H04L7/08 , H04J3/06
摘要： PURPOSE:To omit a frame synchronizing protection circuit in an intra-station interface by allowing an interface of a transmission line to send a frame pattern while revising always into a correct pattern during the frame synchronization. CONSTITUTION:A part surrounded by one-dashed chain lines at the left side in figure is a frame synchronizing part of the interface of a transmission line and a frame pattern revision circuit 15 is added thereto. A part at the right side is an intra-station interface and a synchronizing protection circuit 15 is omitted. Then the frame pattern revision circuit 15 recognizes the presence of the establishment of synchronism from a frame synchronizing protection circuit 12 and the content of a frame pattern ROM 14 is written in a frame pattern location during the establishment of synchronism. Since the code error rate of the transmission line in the station is sufficiently smaller than that of the transmission line at the outside of the station, the synchronizing protection circuit of the intra-station interface can be omitted.

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