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61. 发明专利

JPS5881394A SAMPLE MONITORING AND TIME-DIVISION MULTIPLEX SYSTEM 失效
公开(公告)号：JPS5881394A
公开(公告)日：1983-05-16
申请号：JP18075781
申请日：1981-11-11
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HIRAOKA MAKOTO , HANABATAKE TOSHIO , NOMOTO SHINOBU
IPC分类号： H04J3/00 , H04N7/08 , H04N7/081
摘要： PURPOSE:To prevent the repetition and absence of a signal, and to eliminate deterioration of a regenerated signal by providing a means of discriminating whether the number of samples of a signal such as an aural signal to be inserted into a transmission frame is within a prescribed range or not. CONSTITUTION:An inhibiting and inserting circuit INC is applied with a horizontal synchronizing signal HS and an aural sample clock SP to inhibit or insert a synchronizing signal applied to a control part CONT. This inhibiting and inserting circuit INC has a delay circuit, flip-flop, and counter, which monitors the number of samples of an aural signal to be inserted into a transmission frame; when more samples than prescribed are to be inserted, synchronizing codes are inserted forcibly to insert an aural signal of samples less than prescribed into the transmission frame invariably, and when the period of an extracted horizontal synchronizing signal HS is short and an encoded aural signal is inserted repeatedly, the insertion of synchronizing codes is inhibited.

62. 发明专利

JPS5836052A PARALLEL DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JPS5836052A
公开(公告)日：1983-03-02
申请号：JP13369981
申请日：1981-08-26
申请人： FUJITSU LTD
发明人： HIRAOKA MAKOTO , HANABATAKE TOSHIO
IPC分类号： H04L25/02 , H04J3/06 , H04L25/14
摘要： PURPOSE:To transmit high-speed data through a low-speed data transmission line by separating the high-speed data into plural low-speed data and transmitting them in parallel together with added frame synchronizing signals, and synthesizing them into the high-speed data on a reception side. CONSTITUTION:At a transmitting data terminal station 1, high-speed data 2 is inputted to a separating circuit 3 for separating the input data, bit by bit, into plural data cyclically. In the figure, the high-speed data 2 is separated into five low-speed strings 5-9. Those low-speed data strings 5-9 are given frame synchronizing signals by a frame appending circuit 10 and then transmitted to a receiving data terminal station 12 through low-speed transmission lines 11-1- 11-5. The separated data received by memory circuits 13-1-13-5 through the low-speed transmission lines are inputted through frame detecting circuits 14-1- 14-5 to a synthesizing circuit 16, which reconstitutes the original high-speed data 2.

63. 发明专利

JPS57178591A MONITORING SYSTEM BY TV VIDEO 失效
公开(公告)号：JPS57178591A
公开(公告)日：1982-11-02
申请号：JP6336981
申请日：1981-04-28
申请人： FUJITSU LTD
发明人： NISHIZAWA MITSUJI , TOKIMASA SATORU , OOTA KOUICHI , HIRAOKA MAKOTO
IPC分类号： G08B21/00 , H04N7/18

64. 发明专利

JPS57160242A VARIABLE LENGTH CODE DECODING CIRCUIT 失效
公开(公告)号：JPS57160242A
公开(公告)日：1982-10-02
申请号：JP4562381
申请日：1981-03-30
申请人： FUJITSU LTD
发明人： HANATA TOSHIO , HIRAOKA MAKOTO
IPC分类号： H03M5/04 , H04B1/66 , H04B14/04 , H04L23/00 , H04L25/45
摘要： PURPOSE:To decode a variable length code with simple circuit costitution by providing a detecting circuit for a synchronizing signal on the input side of a buffer memory, and storing the synchronizing signal in a buffer memory by fixing the starting position of the synchronizing signal at the starting position of eight bits. CONSTITUTION:A variable length serial signal is inputted to a buffer memory part 6 through a bipolar to unipolar conversion part 5. In the memory part 6, the input signal is converted by a series-parallel converting circuit 61 into a 16-bit parallel signal, which is inputted to a synchronizing signal detecting circuit 64 while the high-order a low-order 8-bit signals are inputted to FFs 62A and 62B, whose outputs are inputted to FFs 63A and 63B. When the starting bit of the synchronizing signal is positioned at the starting part of the high-order eight bits, the circuit 64 supplies the output signal to a frequency dividing circuit 65. The circuit 65 divides the frequency of a clock signal by 16 to supply the resulting signal to the FFs 63A and 63B, and parallel data is inputted to buffer memories 66A and 66B successively by 16 bits at every time. The data stored in memories 66A and 66B are read out alternately to be supplied to a variable length code decoding part 7 as 8-bit parallel signals.

65. 发明专利

JPS57103474A PULSE PERIOD MONITOR CIRCUIT 失效
公开(公告)号：JPS57103474A
公开(公告)日：1982-06-28
申请号：JP17956380
申请日：1980-12-18
申请人： FUJITSU LTD
发明人： HIRAOKA MAKOTO , HANATA TOSHIO
IPC分类号： H04N5/04 , H04N17/00
摘要： PURPOSE:To stabilize monitoring of a synchronizing signal, by driving two retrigger monostable multivibrators by the synchronizing signal and by operating AND between their output signals and the synchronizing signal. CONSTITUTION:In case that monostable multivibrators MM17 and MM28 are driven by a rise pulse 15 of a synchronizing signal 14 inputted from an input terminal 1, output waveforms of multivibrators MM17 and MM28 are shown in figures 16 and 17 when an output pulse width T1 of the multivibrator MM17, and output pulse width T2 of the multivibrator MM28, and a period T of the synchronizing signal satisfy T1

66. 发明专利

JPS5730452A Variable-length code transmission system 失效
标题翻译：可变长度代码传输系统
公开(公告)号：JPS5730452A
公开(公告)日：1982-02-18
申请号：JP10458880
申请日：1980-07-30
申请人： Fujitsu Ltd
发明人： FUJITA KENGO , MATSUDA KIICHI , HIRAOKA MAKOTO , HONMA TOSHIHIRO , FUKUDA YUTAKA
IPC分类号： H04L23/00 , G06F13/00 , H03M7/42 , H04B14/04
CPC分类号： H03M7/42
摘要： PURPOSE:To save hardware greatly by outputting variable-length codes, word by word, by employing a code converting means of converting fixed-length codes into variable-length ones and also outputting the variable-length codes in a shifted state. CONSTITUTION:When a fixed-length code is inputted, a code converting circuit 11 outputs a variable-length code corresponding to the code, and an output signal shifted by the extent which corresponds to a shift signal from a control circuit 12 is inputted to an eight-bit shift register 7 and a selecting circuit 8. The 1st variable- length code is not shifted, and an effective-bit set register 9 inputs one bit of the variable-length code, for example; when the next fixed-length code is inputted, a shift-1 signal is supplied to a shift control input, so the circuit 11 outputs the variable-length code shifted by one bit to input an effective bit to the register 9. Thus, the shift control varies successively to effective bits to the register 9 eight times, to that an output is generated through an output register 10.
摘要翻译：目的：通过使用将固定长度代码转换成可变长度代码的代码转换装置，并逐行输出可变长度代码，大大地输出可变长度代码来节省硬件。构成：当输入固定长度代码时，代码转换电路11输出与代码相对应的可变长度代码，并将与来自控制电路12的移位信号相对应的程度移位的输出信号输入到八位移位寄存器7和选择电路8.第一可变长度码不被移位，有效位设置寄存器9例如输入可变长度码的一位; 当输入下一个固定长度代码时，向移位控制输入端提供偏移-1信号，因此电路11输出移位了一位的可变长度代码，以将有效位输入到寄存器9.因此，移位控制连续变化到寄存器9的有效位八次，通过输出寄存器10产生输出。

67. 发明专利

JPS56114044A CODE CONVERTING CIRCUIT 失效
公开(公告)号：JPS56114044A
公开(公告)日：1981-09-08
申请号：JP1726180
申请日：1980-02-15
申请人： FUJITSU LTD
发明人： FUJITA KENGO , MATSUDA KIICHI , HIRAOKA MAKOTO , HONMA TOSHIHIRO , FUKUDA YUTAKA
IPC分类号： H03M5/04 , G06F5/00 , H03M7/00 , H03M7/40 , H04L23/00
摘要： PURPOSE:To ease a request for speed to a circuit component element, by carrying out a detection of word length over n words and then controlling a matrix within the n basic time slot to obtain an output in case the fixed length code is converted into the variable length code. CONSTITUTION:The input data having a fixed length is applied to the matrix MT11. The MT11 turns the fixed length code data so that a coincidence is obtained between the highest-rank bit of the output of the MT11 and the head of the next variable length code excepting the vairable length code that is through with the process already in the preceding action among the input fixed length code data by the input of the first basic clock CK and under the control of the control circuit 13. The vairable length code data of a word of the higher-rank bit in the MT11 is read into the FF14. At the same time, the word length detecting circuit 12 performs a word length detection for the output of the TM11 over n words. When the next basic CK is supplied, the contents of the FF14 is read into the FF16. The contents of the FF16 is read by the next basic CK to deliver the data composed of a variable length code.

68. 发明专利

JPS5452439A ERROR DETECTION SYSTEM 失效
公开(公告)号：JPS5452439A
公开(公告)日：1979-04-25
申请号：JP11865577
申请日：1977-10-04
申请人： FUJITSU LTD
发明人： NAKABASHI KENZOU , HIRAOKA MAKOTO
IPC分类号： G06F11/10
摘要： PURPOSE:To detect an operation error easily in an ON-line mode, by inserting a parity check bit signal as a substitute for an input signal from a parity check bit generating circuit during an error check in order to make a parity check. CONSTITUTION:By receiving five bits except the lowest bit, parity check bit generating circuit 3 supplies parity check bit signal PO with lowest bit P6 to switch circuit 4. Now, circuit 4 consisting of logical gate circuits 5...7 is controlled by control signal S1, either one of inputs is sent to checked device 2, and parity check circuit 9 is provided to the output side of device 2. As a result, a parity check bit signal as a substitute for an input signal is inserted from circuit 3 during an error check in order to make a parity check, thereby detecting the operation error of the digital device easily in an ON-line mode.

69. 发明专利

JPS5421220A DITAL SIGNAL COMMUNICATION SYSTEM 失效
公开(公告)号：JPS5421220A
公开(公告)日：1979-02-17
申请号：JP8623577
申请日：1977-07-19
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKAHASHI OSAMU , NAKABASHI KENZOU , HIRAOKA MAKOTO , YASUDA HIROSHI
IPC分类号： H04N7/12 , H04B1/00 , H04L7/00 , H04L13/08
摘要： PURPOSE:To prevent overflow, to realize stable opration at all times and to increase the video quality, by providing n sets (n >= 2) of frame synchronous location identifying signals S at a plural number of locations in a digital signal.

70. 发明专利

JPS5238811A VIDEO SIGNAL MULTIPLEX TRANSMITTING SYSTEM 失效
公开(公告)号：JPS5238811A
公开(公告)日：1977-03-25
申请号：JP11372075
申请日：1975-09-22
申请人： FUJITSU LTD
发明人： TAKAHASHI OSAMU , NAKABASHI KENZOU , HIRAOKA MAKOTO
IPC分类号： H04N7/08 , H04J3/16 , H04N7/00 , H04N7/081 , H04N7/12 , H04N19/50
摘要： PURPOSE:To improve the quality of picture by transmitting and selecting the occupied pattern having greater rate of transmitting lines occupied depending on the channel carrying much data, in case that coded and time sharing transmission is performed.

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