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1. 发明专利

JPH0570353B2 失效
公开(公告)号：JPH0570353B2
公开(公告)日：1993-10-04
申请号：JP9619883
申请日：1983-05-31
申请人： FUJITSU LTD
发明人： HANABATAKE TOSHIO , WADA NOBUYUKI , YAMAUCHI TOSHUKI
IPC分类号： H04N5/10

2. 发明专利

JPH04261334A POWER TRANSMISSION LINE MONITORING SYSTEM 失效
公开(公告)号：JPH04261334A
公开(公告)日：1992-09-17
申请号：JP2205691
申请日：1991-02-15
申请人： FUJITSU LTD
发明人： KIYONAGA TETSUYA , HANABATAKE TOSHIO
IPC分类号： H02J3/00 , H02J13/00 , H04B10/00 , H04B10/035 , H04B10/077 , H04B10/275 , H04B10/29 , H04B10/508 , H04B10/54 , H04B10/548 , H04B10/572 , H04B10/58 , H04Q9/00
摘要： PURPOSE:To realize a coherent light utilized transmission line monitoring system which has no decrease in receiving sensitivity caused by a distortion of an optical signal waveform due to a refractive index change of an optical fiber accompanying the elongation of an optical ground wire(OPGW) when the OPGW is lightened in the system using the OPGW. CONSTITUTION:A coherent light transmission monitoring system in which an oscillation frequency of a transmission light source is so controlled that signal spectrum positions of terminals of iron towers are not superposed by an optical loop network having a central monitor center having a coherent light transmitter having a plurality of transmission light sources controlled at a frequency interval as a frequency reference and a coherent light receiver having a function of selectively receiving an information signal from a light transmission terminal disposed at each iron tower and the iron tower connected to the center in a loop state by an optical fiber so that the loop is composed for all lights without optoelectric conversion to raise its reliability.

3. 发明专利

JPH02285789A CODER AND DECODER 失效
公开(公告)号：JPH02285789A
公开(公告)日：1990-11-26
申请号：JP10691089
申请日：1989-04-26
申请人： FUJITSU LTD
发明人： WADA NOBUYUKI , HANABATAKE TOSHIO , SAKATA TAKASHI , KAWAKADO KOSUKE , SAITO FUMIHIKO
IPC分类号： H04N19/00 , H04N9/64 , H04N11/04 , H04N19/42 , H04N19/423 , H04N19/80 , H04N19/85
摘要： PURPOSE:To reduce the circuit scale and to prevent deterioration in the characteristic of an output signal by correcting a difference between a 1st delay time and a 2nd delay time by retarding the clock signal fed to one conversion means. CONSTITUTION:A picture signal is decomposed and 1st and 2nd analog signals are obtained. A prescribed frequency component is extracted with a 1st delay time in a 1st extraction means 111 from the 1st analog signal. The prescribed frequency component is read in a 1st conversion means 115 and coded synchronously with the 1st clock signal outputted from a clock signal output means 113. A prescribed frequency component of the 2nd analog signal is extracted by a 2nd extraction means 112 with a 2nd delay time longer than the 1st delay time. The prescribed frequency component is read by a 2nd conversion means 117 and coded synchronously with the 2nd clock signal delayed by a difference between the 1st and 2nd delay times and coded.

4. 发明专利

JPH02274032A VIDEO SIGNAL FREQUENCY TRANSMITTING METHOD 失效
公开(公告)号：JPH02274032A
公开(公告)日：1990-11-08
申请号：JP9581889
申请日：1989-04-14
申请人： FUJITSU LTD
发明人： SAKATA TAKASHI , HANABATAKE TOSHIO , WADA NOBUYUKI , KAWAKADO KOSUKE , SAITO FUMIHIKO
IPC分类号： H04N19/00 , H04L7/00 , H04L7/10 , H04L25/49 , H04N19/42 , H04N19/423 , H04N19/70 , H04N19/85 , H04N19/91
摘要： PURPOSE:To miniaturize the circuit scale by reproducing a sampling clock synchronized with the sampling clock of a transmission side on a reception side. CONSTITUTION:In order to reproduce a sampling clock synchronized with the sampling clock of the transmission side on the reception side, a signal obtained by bringing the horizontal synchronizing signal of a video signal to 1/M frequency division by a 1/M frequency divider 6 for the purpose of transmitting the reference frequency of a video signal is used. In this state, the violation is given to the CMI code rule of a CMI encoding part 3 by a code rule violating means 7, and executed by detecting a violation code by a violation code detecting means 8 from a CMI code decoding means 7. Subsequently, based on the detected code as a reference, the sampling clock used by itself is generated by a decoding means 4. In such a manner, in order to transmit the reference frequency of the video signal, it is sufficient that the 1/M frequency divider 6, the code rule violating means 7 and the violation code detecting means 8 are provided.

5. 发明专利

JPH0220187B2 失效
公开(公告)号：JPH0220187B2
公开(公告)日：1990-05-08
申请号：JP19480383
申请日：1983-10-18
申请人： FUJITSU LTD
发明人： HANABATAKE TOSHIO , MAKI SHINICHI
IPC分类号： H04N5/04 , H04L7/02 , H04L7/027 , H04L7/033

6. 发明专利

JPH01231537A PICTURE TRANSMISSION SYSTEM 失效
公开(公告)号：JPH01231537A
公开(公告)日：1989-09-14
申请号：JP5886888
申请日：1988-03-11
申请人： FUJITSU LTD
发明人： HANABATAKE TOSHIO
IPC分类号： H04L7/02 , H04L7/027 , H04N7/00 , H04N11/04 , H04N19/00 , H04N19/59 , H04N19/80 , H04N19/85
摘要： PURPOSE:To omit a function which controls a buffer circuit or the quantity of the produced data by reducing the Q of a filter of a tank circuit used to a clock regenerating circuit in response to at sampling clock. CONSTITUTION:A clock generating circuit 1 produces a sampling clock synchronous with an input picture signal and a transmission line clock. These clocks are supplied to an A/D converter 3 and an output circuit 4 of a coding circuit 2 for transmission of the coded picture signals. Thus the heat is eliminated but the clock variance rate of a transmitted signal rises up by a fact that the sampling clock is produced from the input picture signal. In this respect, the Q of a filter set in a tank circuit of a clock reproducing circuit 6 is reduced at the reception side in accordance with the sampling clock. Thus the selection degree is increased for the transmission line clock and a receiving circuit 5 works on the transmission line clock reproduced by the circuit 6. Then it is possible to omit a function which controls a buffer circuit or the quantity of the produced data.

7. 发明专利

JPH01218233A MULTIPLEXING TRANSMITTING METHOD AND SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH01218233A
公开(公告)日：1989-08-31
申请号：JP4339988
申请日：1988-02-26
申请人： FUJITSU LTD
发明人： HANABATAKE TOSHIO
IPC分类号： H04J3/06
摘要： PURPOSE:To simplify a hardware such as a clock generating system in multiplexing transmission and to identify a transmitting signal by adding a signal used for synchronization and identifying a transmitting signal to a transmitting signal to be multiplexed. CONSTITUTION:Converting circuits 131-13n corresponding to respective channels add a second signal to identify and synchronize for a transmitting signal to a transmitting signal. These signals of respective channels are multiplexed and sent to a transmission line with a multiplexing circuit 14. The transmitted signal is extracted classified by the channel and a signal for hunting is generated at the time of asynchronous with synchronizing detecting circuits 601-60n. A channel selecting output means 69 inputs the output of the synchronizing detecting circuits 601-60n designated by a channel selecting signal from a channel selecting signal output means 69 to a hunting circuit 90. The hunting circuit 90 gives the output to a channel extracting circuit 57 and generates synchronization.

8. 发明专利

JPS62220082A PICTURE ENCODING DEVICE 失效
公开(公告)号：JPS62220082A
公开(公告)日：1987-09-28
申请号：JP6295286
申请日：1986-03-20
申请人： FUJITSU LTD
发明人： HANABATAKE TOSHIO
IPC分类号： H04N19/00
摘要： PURPOSE:To reduce the whole of information quantities, and to reduce the capacity of a buffer memory, by providing a quantization characteristic switching circuit which makes small a quantizing step at the center part of a picture, and makes large the quantizing step at the peripheral part of the picture. CONSTITUTION:An area detection circuit 8 identifies the center part of the picture from the peripheral part of the picture by counting the synchronizing signal of a television signal. The identification signal of the detection circuit 8 is supplied to a quantization characteristic switching circuit 22, and switches a quantization characteristic at the center part, and the peripheral part of the picture. In other words, quantization with a small step and high accuracy is performed at the center part of the picture, and the quantization with a large step and low accuracy is performed at the peripheral part. By constituting a device in such a way, the whole of the information quantities can be reduced, thereby, the capacity of a buffer memory 3 can be reduced.

9. 发明专利

JPS62219842A FRAME SYNCHRONIZING EXTRACTING CIRCUIT 失效
公开(公告)号：JPS62219842A
公开(公告)日：1987-09-28
申请号：JP6293486
申请日：1986-03-20
申请人： FUJITSU LTD
发明人： HANABATAKE TOSHIO
IPC分类号： H04L7/08 , H04J3/06
摘要： PURPOSE:To reduce an action speed after a frame synchronizing extracting circuit and to execute the forming with a semiconductor integrated circuit by collating a frame signal and synchronizing a frame pattern after the word synchronization of an nB1c code of a received data input signal is obtained by a serial parallel conversion circuit. CONSTITUTION:A received serial signal is converted to the parallel signal of 9 bits by a serial parallel conversion circuit 14. When a word synchronization is obtained, an 8-bit signal is arranged completely up to the first eighth bits and the nineth bit obtains the complementary level of the seventh bit. Consequently, the output of an exclusive 'OR' circuit 121 always generates a '0' level at the time of the word synchronization and a '1' or '0' level at the time of non-synchronization. By one level to occur at the output, the signal accommodated into a serial parallel conversion circuit is shifted bit by bit at the time of non-synchronization until the synchronization is obtained. A protecting circuit 123, when the non-synchronization detection is continuous by the number of times specified beforehand, executes a bit shifting for the first time. Since the receiving signal to obtain the word synchronization is held by a flip-flop circuit 15 and converted to a parallel signal after the circuit 15, the synchronizing clock may be the circuit operated by the clock to frequency-divide a transmission line clock by a 1/(n+1) frequency-dividing circuit 11, and can be realized by a low speed integrated circuit.

10. 发明专利

JPS6264173A RESET LEVEL TRANSMISSION SYSTEM 失效
公开(公告)号：JPS6264173A
公开(公告)日：1987-03-23
申请号：JP20305685
申请日：1985-09-13
申请人： FUJITSU LTD
发明人： AZUMA HIROKI , HOSOKAWA TAKAHIRO , HANABATAKE TOSHIO
IPC分类号： G01R31/26 , H04N5/04
摘要： PURPOSE:To reproduce a horizontal synchronizing part without distortion by transmitting the horizontal synchronization level of an original signal from the transmission side and reproducing it on the reception side to reset an encoding processing. CONSTITUTION:On the transmission side, the reset value of a synchronizing signal for an optional period within a synchronization period is extracted, a picture signal is encoded, and both are transmitted. On the reception side, a frame header is detected from a received picture frame by a picture frame header detection circuit 6, and at the same time the reset value is extracted. Thereafter, a decoding circuit 7 inserts the reset value into the encoded picture data during a reset period, and decodes the data. A D/A converter 8 D/A- converts the decoded data and reproduces the picture signal. The reset level of the horizontal synchronizing part of the picture signal thus reproduced is equal to the level of the original signal on the transmission side. Therefore, no distortion occurs during the reset period of the picture signal.

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