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61. 发明专利

JPS57157357A COMPILE PROCESSING SYSTEM 失效
公开(公告)号：JPS57157357A
公开(公告)日：1982-09-28
申请号：JP4207481
申请日：1981-03-23
申请人： FUJITSU LTD , PANA FACOM KK
发明人： MATSUBAYASHI JIROU , TAKEYAMA SATORU , YAKABE KAZUYUKI
IPC分类号： G06F9/45 , G06F9/44
摘要： PURPOSE:To increase the processing efficiency at an object program execution, by suppressing register saving to a minimum degree, through the addition of a bit map forming module in a compiler. CONSTITUTION:A bit map forming module 7 provided in a compiler 2 is constituted so that a bit map table 8 can be formed corresponding to registers to be used. A module 6 informs the corresponding register to the module 7 based on the fact that a register giving the change in content is determined during the execution of processing of a program 3, and when the object program 3 corresponding to a source program 1 is produced, a code producing module 5 adds a prologue and an epilogue indicating the saving of content to the object program 3 based on the content of the bit map table 8 produced at the module 7.

62. 发明专利

JPS57139841A INTERRUPTION CONTROL SYSTEM 失效
公开(公告)号：JPS57139841A
公开(公告)日：1982-08-30
申请号：JP2508381
申请日：1981-02-23
申请人： PANA FACOM KK , FUJI FACOM SEIGIYO , KAWASAKI HEAVY IND LTD
发明人： WADA OSAMU , WAKABAYASHI YASUYUKI , ITOU KENJI
IPC分类号： G06F9/48 , G06F13/00 , G06F13/24
摘要： PURPOSE:To reduce a load of a processor of the center side, and to elevate the efficiency of the whole system, by generating an interruption only when contents of a telegram of a state of the other party have been varied, and when a line fault has occurred, when receiving a data. CONSTITUTION:A data D passes through a communication line 1, reaches a line adaptor 2, and is stored in a buffer 3. A detecting circuit 4 has a means for supervising a data in the buffer 3 whenever it is received, and detecting a difference of data contents between a new received data and an old received data. When receiving a data, the detecting circuit 4 checks a difference between the new received data and the old received data in the buffer 3, and sends out an interruption signal 1 to a processor 8 only in case when a variation of the data contents has been detected. Therefore, the processor generates a control signal, transfers a new received data D in the buffer 3 to a data area 6 of a main storage device 7, and after that, processes this received data.

63. 发明专利

JPS57106920A DISPLAY SYSTEM FOR FAULT OF POWER SOURCE 失效
公开(公告)号：JPS57106920A
公开(公告)日：1982-07-03
申请号：JP18307080
申请日：1980-12-24
申请人： PANA FACOM KK
发明人： KUBO MASAFUMI , WATANABE YASUO , ASAJI YOSHIO
IPC分类号： G08B23/00 , G06F1/28 , G08B21/00 , H02J1/00 , H02J9/00
摘要： PURPOSE:To obtain the function of displaying a fault of a power source without increasing the cost of a device, by displaying the fault of the power source by utilizing display devices, etc., provided to a console panel. CONSTITUTION:If the power source of input and output equipment becomes abnormal, that is discriminated by a power source controller 3, whose signal permits a buzzer 4 to sounding and a lamp 6 to turn on, indicating that the input and output equipment is abnormal. When an operator confirms it and presses a buzzer cut switch 5, its signal is inputted to the controller 3 to stop the buzzer and also inputted to a multiplexer 8 to change a common-use number display device A1 over to the side of the controller 3. Further, it is inputted to number display devices A2-A4 to stop their functions. As a result, information on the contents of the abnormality is inputted from the controller 3 to the common-use number display device A1 through the multiplexer 8 to be displayed as a one-digit number.

64. 发明专利

JPS57105040A INSTRUCTION READ-OUT REQUEST SYSTEM 失效
公开(公告)号：JPS57105040A
公开(公告)日：1982-06-30
申请号：JP18228280
申请日：1980-12-23
申请人： PANA FACOM KK
发明人： GOTOU TOSHIO , ASAJI YOSHIO , KOIZUMI NAOKI , TATSUTA HIROBUMI
IPC分类号： G06F9/32 , G06F9/30
摘要： PURPOSE:To read out an instruction at a high speed, by halting read-out of access by a bit of a read-out output of a decoding ROM after read-out of the first word has ended, in an instruction read-out request system having length of >=2 words. CONSTITUTION:When read-out of the first word is ended, an output of an FF102 sets an FF103 through a gate 101, and generates an access request signal MREQ. In this case, if a bit prescribed in advance, of a read-out output of a decoding ROM106 is ''1'', a signal CAN for halting a process of access is generated. This signal CAN passes through an OR gate 104, clears the FF103, halts the process of access before a CPU access permission signal is outputted, and also generates an end signal SRVO without waiting for read-out by a halt request signal.

65. 发明专利

JPS5718094A DATA COPYING SYSTEM FOR DUPLEX MEMORY 失效
公开(公告)号：JPS5718094A
公开(公告)日：1982-01-29
申请号：JP9142880
申请日：1980-07-04
申请人： PANA FACOM KK
发明人： TAKEGAWA TERUAKI , SUZUKI AKIHIKO , NAKA KENICHI , FUTAKI JIYOUICHI
IPC分类号： G06F12/16 , G06F13/18
摘要： PURPOSE:To enable data copy without interrupting on-line, by confirming that the duplex memory is not busy and no access request of CPU is present, reading out data from one memory and writing-in it on another. CONSTITUTION:When a duplex memory is operated in data copy mode, the access request from a central processing device is monitored for busy check and the copy for one memory block's share is made only when the access request with the lowest priority is absent. This is done by a priority discrimination circuit 9. The data write- in from the CPU is made both for the normal and correcting systems, and the data readout is made from only the normal system. At the end of all the area copy of memory, it is informed to the CPU through interruption, and if data error impossible of correction is detected 7, the copy is interrupted to inform it to the CPU through interruption.

66. 发明专利

JPS56145448A COMMON-USE CONTROL SYSTEM 失效
公开(公告)号：JPS56145448A
公开(公告)日：1981-11-12
申请号：JP4754980
申请日：1980-04-11
申请人： PANA FACOM KK
发明人： SHIMIZU YASUO , OGAWA SHINJI , KINOSHITA AKIO , NAKA KENICHI
IPC分类号： G06F11/16 , G06F13/00 , G06F13/40 , G06F15/16 , G06F15/173 , G06F15/177
摘要： PURPOSE:To achieve the effective processing by CPU by providing the function of diagnosing periodically CPUs which correspond to respective couplers, that of informing other couplers of the fault occurence of CPU, and that of rearranging the contents of its own reserve register. CONSTITUTION:To CPU buses 3-1-3-3 of CPUs 1-1-1-3 of the multisystem computer system, couplers 2-1-2-3 are connected and at the intersections of buses 3-1-3-3 and common-use buses 4-1 and 4-2, bus switches S11-S32 are provided. Those couplers 2-1-2-3 are provided with microprocessor 7, bus control circuit 8, sequence control circuit 9, and data-reception/transmission control circuits 10 and 11, and main memory 13 of the processor is further connected via microprocessor bus 12. Under the control of processor 7, the fault of one of CPUs 1-1-1-3, when occurring, is reported to other couplers 2-1-2-3 to rearrange the contents of its own reserve register, thereby making the processing of other CPUs effective.

67. 发明专利

JPS56145411A PROGRAM LOAD SYSTEM 失效
公开(公告)号：JPS56145411A
公开(公告)日：1981-11-12
申请号：JP4754280
申请日：1980-04-11
申请人： PANA FACOM KK
发明人： SHIMIZU YASUO , OGAWA SHINJI , KINOSHITA AKIO
IPC分类号： G06F1/00 , G06F9/445 , G06F15/177
摘要： PURPOSE:To facilitate the modification of the program of a subordinate computer by loading a program into the storage device of the subordinate computer by way of the storage device of a host computer. CONSTITUTION:Transfer control circuit 9-i is a direct storage access DMA controller and has a storage address register and byte count register in it. The contents of this storage address register indicate the starting address of the main storage of a microprocessor, and those of the type count register the transfer type length. Microprocessor main storage 10-i is composed of RAM. Starting circuit 11-i has an iPL flag in it; when the initial loading (iPL) flag is set to ''1'', initial program loading to main storage 10-i is performed and when the iPL flag is changed to ''0'', processor 12-i starts executing the loaded program.

68. 发明专利

JPS56143073A MULTIPROCESSOR PROCESSING SYSTEM 失效
公开(公告)号：JPS56143073A
公开(公告)日：1981-11-07
申请号：JP4702180
申请日：1980-04-10
申请人： PANA FACOM KK
发明人： MARUOKA HIROSHI , IMAI KUNIKAZU , SUZUKI AKIHIKO , ASOGO HIROYUKI
IPC分类号： G06F11/16 , G06F13/00 , G06F13/40 , G06F15/16 , G06F15/173 , G06F15/177
摘要： PURPOSE:To increase reliability of an entire system, by providing a bus of CPU system with a constitution controller monitoring the state of CPU and a constitution processor controlling a switching device located at the cross point between the bus of a peripheral device system and the bus of the CPU system. CONSTITUTION:The buses 2-1-2-m of CPUs 1-1-1-m system are provided with the constitution controllers 7-1-7-m which make reception/transmission of information among CPUs. Further, the constitution processor 8 having the status monitor 11 which monitors the state of the power supply control section 13 making application/ cut-off of the power supply to the PF system, connection switching section 9 controlling the switching devices SW11-SWmn provided at the cross point between the CPU system bus and the peripheral device PF system buses 5-1-5-n, and the PF system and the switching device SW, is provided. The monitor section 11 stores the preceding status information of PF and SW to the memory, and compares the memory information and the status information of the newest PF or SW. If they are in disagreement, it is informed to the data processing section of the stored program control by interruption to switch SW and cut-off of the power supply of PF, to avoid influence of one failure on other parts.

69. 发明专利

JPS56140431A POWER SUPPLY CONTROLLING SYSTEM OF MULTIPROCESSOR PROCESSING SYSTEM 失效
公开(公告)号：JPS56140431A
公开(公告)日：1981-11-02
申请号：JP4370980
申请日：1980-04-03
申请人： PANA FACOM KK
发明人： MARUOKA HIROSHI , IMAI KUNIKAZU , SUZUKI AKIHIKO , ASOGO HIROYUKI
IPC分类号： H02J1/00 , G06F1/26 , G06F1/30 , G06F11/16 , G06F15/16 , G06F15/177
摘要： PURPOSE:To reduce the load and the decision of the operator, by controlling power supply units, which are divided correspondingly to function units, by the power supply control general controlling part, which has a stored program SP control device, to cope with power supply abnormality. CONSTITUTION:This system is provided with the connection switching part, which controls independently switching devices provided at intersections between plural CPU system busses and peripheral device PF system busses, and the configuration processing device which has power supply controlling part 13 for power supply and cut-off of respective devices and state monitoring part 11 for monitoring of the state of the switching device. SP controlling processor 18 of monitoring part 11 controls general control device 19 for power supply control, and device 19 monitors power supply states of main power sources 15-1 and 15-2 and auxiliary power supply units 16-0- 16-mn provided for every switching device and controls directly cut-off and supply of respective power sources at the fault time. Device 19 controls respective PF system power supply controlling parts 14, power supply controlling part 20 for remote control, and power supply controlling part 21 for auxiliary input/output units through general control auxiliary device 13. These controls are performed without intervention of the operator by SP.

70. 发明专利

JPS562764A INFORMATION TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPS562764A
公开(公告)日：1981-01-13
申请号：JP7956479
申请日：1979-06-22
申请人： PANA FACOM KK
发明人： YAMAGUCHI TAHEI , HAIDA HIROTOSHI , SATOU NOBUSATO
IPC分类号： G06F13/36 , G06F13/37 , H04L29/08
摘要： PURPOSE:To reduce the number of signal busses and shorten the processing time for bus occupation, by giving bus occupation permission to a transmission and receiving unit requesting information transfer when information is transferred between plural transmission and receiving units connected on common signal busses. CONSTITUTION:Plural transmission and receiving units 2-i are connected to confirmation signal line 7, transmission request signal line 5, and the first and the second permission signal lines 6-1 and 6-2 of common signal busses, and this unit 2-i is provided with transfer request signal REQ generating circuit part 11, confirmation signal ACK generating circuit part 12, FF13, and AND circuits 15 and 16 forming the delay line. When unit 2-i issues transfer request signal REQ, FF13 is set to store issuance of signal REQ, and permission signal PRM based on signal REQ from the bus control unit is received, and circuit 16 is turned on to generate confirmation signal ACK from circuit 12. When signal REQ is transferred to the second permission signal line 6-2, FF13 is reset, and circuit 15 is turned on, and signal PRM is transferred to the next unit 2-i, thus shortening the processing time.

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