专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明专利

JPH06230991A METHOD AND APPARATUS FOR COMPUTATION OF INVERSE NUMBER OF ARBITRARY ELEMENT IN FINITE FIELD 失效
公开(公告)号：JPH06230991A
公开(公告)日：1994-08-19
申请号：JP25329493
申请日：1993-10-08
申请人： SAMSUNG ELECTRONIC
发明人： I JIYON FUAN
IPC分类号： G06F7/552 , G06F7/72 , G06F11/10 , G06F17/10 , G06F15/31
摘要： PURPOSE: To calculate the inverse number of an arbitrary element belonging to a finite field GF (2 ) having a primitive element and a permanent element for the inverse number and multiplication of the primitive element in a simple circuitry with low costs. CONSTITUTION: This method includes a process for comparing an arbitrary element with a permanent element, process for calculating the permanent element as the inverse number of the arbitrary element when the arbitrary element is equal to the permanent element, step for repeating multiplication for repeatedly multiplying the primitive element and outputting a first element, and repeatedly multiplying the inverse number of the primitive element and outputting a second element when the arbitrary element is not equal to the permanent element after initialization by the permanent element until one of the first and second elements is equal to the above mentioned arbitrary element, and step for calculating the second element as the inverse number of the arbitrary element when the first element is equal to the arbitrary element, and calculating the first element as the inverse number of the arbitrary element when the second element is equal to the arbitrary element.

52. 发明专利

JPH06224695A DIGITAL SIGNAL PROCESSOR 失效
公开(公告)号：JPH06224695A
公开(公告)日：1994-08-12
申请号：JP20481792
申请日：1992-07-31
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HAYASHI KENICHIRO , KAGEYAMA TEIJI , INOUE HIDEO , UEHATA HIDEYO , TATSUDO BAUZAA , YASUMOTO YOSHIO
IPC分类号： H03H17/02 , G06F17/10 , H03H17/06 , G06F15/31
摘要： PURPOSE:To reduce the number of bits required for transmission of the signal of an operation circuit to suppress the extension of the circuit scale by subjecting a signal subjected to operation processing and a signal, which is obtained by subjected the signal to time base shift processing, to bit shift addition processing. CONSTITUTION:When an input signal is an 8-bit digital signal, the 8-bit signal inputted to an input terminal 1 is subjected to time base multiplexing processing by a bit division time base multiplexing circuit 2 after being divided into, for example, a high-order signal of four high-order bits and a low-order signal of four low-order bits. The input signals having different kinds of delay time for the respective input signals subjected to time base multiplexing processing by difference of the number of delay circuits which the signal passes, are inputted to coefficient circuits 4a to 4d and are multiplied by some coefficients and are added by an adding circuit 5. The addition result for high-order signals and that of low-order signals which are inputted with a time deviation between them are synthesized to restore a desired operation result in an operation result restoring circuit 5, and it is outputted to a output terminal 7.

53. 发明专利

JPH06223095A METHOD AND DEVICE FOR DERIVING POLYNOMIAL SYSTEM 失效
公开(公告)号：JPH06223095A
公开(公告)日：1994-08-12
申请号：JP933393
申请日：1993-01-22
申请人： CANON KK
发明人： IWAMURA KEIICHI
IPC分类号： G06F11/10 , G06F17/10 , H03M13/00 , G06F15/31
摘要： PURPOSE:To quickly obtain a minimum polynomial system which generates a given multi-dimensional array with respect to decoding of an algebraic geometrial code. CONSTITUTION:An array storage means where a given multi-dimensional array (u) is stored, first and second polynomial storage means where a polynomial system F to be obtained and another polynomial system G different from the pertinent polynomial system F are stored respectively, a first operation means which executes operation f =z .f --(dfn /dfm .z .g for polynomials f and g stored in the first and second polynomial storage means respectively, a second operation means which executes operation dfn+1 =SIGMAfm .um+n+1-s of the operated polynomial f =SIGMAfm .zm and the stored multi-dimensional array (u), and a control means which in parallel controls the access to first and second polynomial storage means and lets the address of this access depend on the degree of the polynomial f are provided.

54. 发明专利

JPH06215019A ARITHMETIC UNIT AND PARALLEL ARITHMETIC UNIT SYSTEM 失效
公开(公告)号：JPH06215019A
公开(公告)日：1994-08-05
申请号：JP2334693
申请日：1993-01-18
申请人： SONY CORP
发明人： FUJITA HIROYUKI
IPC分类号： G06F7/00 , G06F17/10 , G06F15/31
摘要： PURPOSE:To avoid the collision of data outputted from respective parts on a data bus or the delay of processing and to accelerate the repeated processing of the arithmetic of the sum of products by improving efficiency for using the respective parts. CONSTITUTION:A latch 12a is arranged before a multiplier 12b. The multiplier 12b supplies the product of an output from the latch 12a and data from an input terminal 13 to a multiplexer 12c. The multiplier 12b supplies the product through the multiplexer 12c and a latch 12d to a serially arranged an arithmetic and logic circuit 12e. The arithmetic and logic circuit 12e calculates the sum of products and outputs the result from an output terminal 14. The latch 12a, multiplexer 12c and arithmetic and logic circuit 12e are respectively controlled by control signals from input terminals 16, 17 and 18.

55. 发明专利

JPH06208553A METHOD AND PROCESSOR FOR SIGNAL PROCESSING 失效
公开(公告)号：JPH06208553A
公开(公告)日：1994-07-26
申请号：JP206093
申请日：1993-01-08
申请人： KAWASAKI STEEL CO
发明人： DANKI RIYOUICHI
IPC分类号： G06F15/18 , G06F17/10 , G06G7/60 , G06N99/00 , G06F15/31
摘要： PURPOSE:To provide the method and device for signal processing which can perform optional numerical calculation processing and signal processing with practical precision by using a limited scale of hardware. CONSTITUTION:As for an addition result obtained by adding a constant to an input signal, a width multiplication arithmetic part A calculates width multiplication terms less than a multiplier required to obtain requested precision and the arithmetic result of an expansion expression arithmetic part C which adds all multiplication results, obtained by multiplying the respective width multiplication terms by a weight coefficient defined previously by a coefficient derivation part 2, by an adder 1 is connected as a fixed information quantity to a next stage; while constants and weight coefficients are determined by the coefficient derivation part 2 in order by an automatic generating method for one function which consists of plural connected processing units as one unit and a compound function automatic generating method constituted by connecting plural units, the addition result is repeated as an input signal for next time to structure a specific Taylor arithmetic system.

56. 发明专利

JPH06202750A NUMERICAL ANALYSIS METHOD 失效
公开(公告)号：JPH06202750A
公开(公告)日：1994-07-22
申请号：JP34794492
申请日：1992-12-28
申请人： HITACHI LTD
发明人： WATANABE MASATOSHI , IKEGAWA MASAHIRO
IPC分类号： G01M9/00 , G06D5/00 , G06F17/10 , G06F15/31
摘要： PURPOSE:To shorten calculation time and to reduce a storage capacity by dividing the whole of an area into areas and reducing the dimensions to analyze the areas in the case of areas which can be approximated to lower dimensions. CONSTITUTION:With respect to formation of a compression wave due to, for example, plunge of a vehicle into a tunnel, its propagation, and analysis of its discharge to a tunnel exit shell, an area 31 is an entrance area until the vehicle plunges into a tunnel, and an area 32 in an area around the vehicle. The compression wave is generated when the vehicle included in the area 32 plunges into the tunnel. The compression wave is generated three-dimensionally; and when the vehicle velocity is smaller than the acoustic velocity, the compression wave proceeds in the tunnel more quickly than the vehicle because the compression wave proceeds forward at the acoustic velocity. Since the compression wave proceeding in the tunnel can be approximated as a one-dimensional phenomenon, a tunnel area 33 can be subjected to one-dimensional analysis. As the result, the storage capacity is made smaller and the calculation time is reduced in comparison with those for three-dimensional analysis of all of areas.

57. 发明专利

JPH06161484A DELAY DEVICE 失效
公开(公告)号：JPH06161484A
公开(公告)日：1994-06-07
申请号：JP33510892
申请日：1992-11-19
申请人： ROLAND CORP
发明人： NOZAWA NAOYA
IPC分类号： G10H1/00 , G06F17/10 , G10H3/24 , G10K15/12 , G06F15/31
摘要： PURPOSE:To decrease the frequency of access to a random access memory and also decrease the number of multiplication coefficients. CONSTITUTION:A delay signal is read out of an address corresponding to an intermediate tap of the delay line 24 composed of the random access memory and a multiplier 32 multiplies it by a specific coefficient; and the multiplication value is added by an adder 26 to an input signal on the input side of the delay line 24 and the result is inputted to the delay line 24.

58. 发明专利

JPH06110916A SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH06110916A
公开(公告)日：1994-04-22
申请号：JP25839392
申请日：1992-09-28
申请人： SHARP KK
发明人： NAKAMURA SATOJI , SUDO KENGO , II HIROSHI
IPC分类号： H03M7/30 , G06F17/10 , G06F15/31
摘要： PURPOSE:To obtain a circuit in which an entire circuit scale is small, and the high speed of a signal processing can be attained by allowing a digital signal processing circuit for an arithmetic operation processing and the digital signal processing circuit for a bit processing operating share the signal processing, and simultaneously operating the signal processing in parallel. CONSTITUTION:A signal processing circuit 10 is constituted of a DSP(digital signal processor) 13 for the arithmetic operation which operates the arithmetic operation, DSP 11 for the bit processing which operates the bit arithmetic operation, interfaces 14 and 17 for connecting this circuit with outside equipments, and buffer memories 12, 15, and 16 for transferring data between those devices. Then, the DSP 11 for the bit processing and the DSP 13 for the arithmetic operation are equipped with each program ROM (RAM), program counter, and each kind of register, etc., and each data processing can be simultaneously operated in parallel. Thus, the high speed processing can be attained, the operation clocks, power consumption, and power supply voltage of a semiconductor integrated circuit can be reduced, and the integrated circuit can be miniaturized.

59. 发明专利

JPH06103299A COMPUTING ELEMENT FOR SUM OF PRODUCTS 失效
公开(公告)号：JPH06103299A
公开(公告)日：1994-04-15
申请号：JP24918792
申请日：1992-09-18
申请人： HITACHI LTD
发明人： YANO TAKASHI , KOJIMA KOJI
IPC分类号： G06F17/10 , G06F15/31
摘要： PURPOSE:To provide a product summing computing element capable of rapidly accumulating multiplied results. CONSTITUTION:Partial products as the results of logical operation between multipliers and multiplicands which are obtained by a partial product generating circuit 3 and the halfway result of accumulation up to just before the accumulation stored in an accumulation register 5 are collectively added by a single Wallace tree 4, as the result, carry is reserved, and for the longest digits, an added result expressed as the sum of plural bits is inputted to a register 6 as a new accumulation halfway result. Thereby, accumulation in summing of product operation accompanied with accumulation can rapidly be executed. Accumulation is operated plural times in order to obtain one operation result output.

60. 发明专利

JPH0689301A ADDRESS GENERATOR, VARIABLE-LENGTH FIELD-ADDRESS SEQUENCER AND VARIABLE-LENGTH FIELD COMMUTATOR FOR MULTICHANNEL CIRCULAR BUFFER TYPE PROCESSING 失效
公开(公告)号：JPH0689301A
公开(公告)日：1994-03-29
申请号：JP11196293
申请日：1993-05-13
申请人： SHARP KK , SHARP MICROELECT TECH INC
发明人： MAIKERU EDOWAADO FUREMINGU , ERITSUKU KUREIGU ANDAASON
IPC分类号： G06F12/02 , G06F13/18 , G06F17/10 , G06F15/31
摘要： PURPOSE: To provide a fast address signal generator which supplies a proper address sequence to a memory device in a fast circular buffer type digital signal processing system that can extend its signal processing performance up to a miltiplexer channel. CONSTITUTION: A 1-chip address generator 170 generates a sequence of address signals which are supplied to a memory having plural circular buffers. An address generator chip can process the service requests given from plural channels based on the priority of the requests. The service requests can be received asynchronously with each other and at different speeds. The specific length or the overlapping value of channels can be assigned to each service of requests. Then a continuous pipeline structure is offered to process the service request of the next channel right after the service is over to the request of the first channel.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式