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51. 发明专利

JP2006253634A Processing method of substrate, process for fabricating electronic device and program 有权
标题翻译：基板处理方法，电子设备制作工艺及程序
公开(公告)号：JP2006253634A
公开(公告)日：2006-09-21
申请号：JP2005278843
申请日：2005-09-26
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI , IWASAKI KENYA
IPC分类号： H01L21/768 , H01L21/02 , H01L21/302
CPC分类号： H01L21/02063 , H01L21/0206 , H01L21/31116 , H01L21/67161 , H01L21/67167 , H01L21/6719 , H01L21/67201 , H01L21/76814 , Y10S438/906
摘要： PROBLEM TO BE SOLVED: To provide a process for fabricating an electronic device in which control of the quantity of a surface damage layer being removed can be carried out easily while preventing deterioration in wiring reliability. SOLUTION: A SiOC based low permittivity interlayer insulating film material is deposited on a capacitor 105 formed on the surface of a wafer W or a low permittivity interlayer insulating film 106 composed of an organic polymer based coating type low permittivity interlayer insulating film material is deposited (A), a photoresist layer 108 having an opening 107 is formed (B), a via hole 109 is bored by etching the low permittivity interlayer insulating film 106 through RIE processing (C), surface of the via hole 109 covered with a false SiO 2 layer 110 is exposed to the atmosphere of mixture gas of ammonia gas, hydrogen fluoride gas and argon gas under a predetermined pressure (D), and the surface of the via hole 109 on which a product 111 is created is heated at a predetermined temperature (E). COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造电子装置的方法，其中可以容易地执行去除的表面损伤层的量的控制，同时防止布线可靠性的劣化。解决方案：在形成在晶片W的表面上的电容器105或由有机聚合物基涂层型低介电常数层间绝缘膜材料构成的低介电常数层间绝缘膜106上沉积SiOC基低介电常数层间绝缘膜材料沉积（A）时，形成具有开口107的光致抗蚀剂层108（B），通过RIE处理（C）蚀刻低介电常数层间绝缘膜106来钻孔通孔109，通孔109的表面被覆盖在预定压力（D）下，将假的SiO 2 SBB层110暴露于氨气，氟化氢气体和氩气的混合气体的气氛中，其中通孔109的表面产品111在预定温度（E）下被加热。版权所有（C）2006，JPO＆NCIPI

52. 发明专利

JP2014112664A Etching method and substrate processing apparatus 有权
标题翻译：蚀刻方法和基板处理装置
公开(公告)号：JP2014112664A
公开(公告)日：2014-06-19
申请号：JP2013224567
申请日：2013-10-29
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI , KUSHIBIKI MASATO , KOIZUMI TADASHI , SONE TAKASHI , YAMASHITA FUMIKO
IPC分类号： H01L21/3065 , C23F4/00 , H01L21/28 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L21/8246 , H01L23/532 , H01L27/105 , H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , G11C11/161 , H01J37/32091
摘要： PROBLEM TO BE SOLVED: To optimize a gas in etching and treating a metal laminated film in which two magnetic layers and an insulating layer are laminated with the insulating layer sandwiched between the two magnetic layers.SOLUTION: There is provided an etching method for etching a multilayer film material including a metal laminated film in which a first magnetic layer, a second magnetic layer, and an insulating layer are laminated with the insulating layer sandwiched between the first magnetic layer and the second magnetic layer. The etching method includes: an etching step of supplying a gas containing C, O, and H into a treatment container to generate plasma, and etching the metal laminated film by the generated plasma; and a treatment step of supplying a gas containing a CFgas into the treatment container to generate plasma, and treating the metal laminated film by the generated plasma.
摘要翻译：要解决的问题：为了优化蚀刻和处理其中两个磁性层和绝缘层与夹在两个磁性层之间的绝缘层层压的金属层压膜的气体。解决方案：提供蚀刻方法多层膜材料包括金属层压膜，其中第一磁性层，第二磁性层和绝缘层被层压，绝缘层夹在第一磁性层和第二磁性层之间。蚀刻方法包括：将含有C，O和H的气体供应到处理容器中以产生等离子体并通过所产生的等离子体蚀刻金属层压膜的蚀刻步骤; 以及将含有CF气体的气体供给到处理容器中以产生等离子体并且通过所产生的等离子体处理金属层叠膜的处理步骤。

53. 发明专利

JP2012204367A Substrate processing method and storage medium 有权
标题翻译：基板加工方法和储存介质
公开(公告)号：JP2012204367A
公开(公告)日：2012-10-22
申请号：JP2011064496
申请日：2011-03-23
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI , KUSHIBIKI MASATO , YAMASHITA FUMIKO
IPC分类号： H01L21/3065
CPC分类号： H01L21/31116 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To provide a substrate processing method capable of preventing the etching rate from lowering when a hole or a trench having a high aspect ratio is formed in an oxide film.SOLUTION: When forming a hole 46 of high aspect ratio in an oxide film 36 which is formed on a wafer W by using a hard mask film 38 consisting of silicon and having an aperture 39, the oxide film 36 corresponding to the aperture 39 is etched by plasma generated from a processing gas containing CFgas and methane gas. Subsequently, reactive products 45 produced during the etching and deposited on the inner surface of the hole 46 in the oxide film 36 is ashed by plasma generated from a processing gas containing oxygen, and the etching and ashing are repeated in this order.
摘要翻译：要解决的问题：提供一种当在氧化物膜中形成具有高纵横比的孔或沟槽时能够防止蚀刻速率降低的衬底处理方法。解决方案：通过使用由硅构成的具有孔39的硬掩模膜38在形成在晶片W上的氧化物膜36中形成高纵横比的孔46时，与孔的对应的氧化膜36 39由从含有气体和甲烷气体的处理气体产生的等离子体进行蚀刻。随后，在蚀刻期间产生的沉积在氧化膜36中的孔46的内表面上的反应产物45被从含有氧的处理气体产生的等离子体等离子体，并且依次重复蚀刻和灰化。版权所有（C）2013，JPO＆INPIT

54. 发明专利

JP2012174850A Substrate processing method, and storage medium 有权
标题翻译：基板处理方法和存储介质
公开(公告)号：JP2012174850A
公开(公告)日：2012-09-10
申请号：JP2011034568
申请日：2011-02-21
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI , SONE TAKASHI , YAMASHITA FUMIKO
IPC分类号： H01L21/3065
CPC分类号： H01L21/32137
摘要： PROBLEM TO BE SOLVED: To provide a substrate processing method by which a hole having a high aspect ratio or the like can be formed in a silicon layer without reducing an etching rate.SOLUTION: The substrate processing method comprises: etching a polycrystalline silicon layer 38 on a wafer by means of bromine cations 45a and bromine radicals 45b in plasma formed from a process gas containing hydrobromic gas, oxygen gas, and nitrogen trifluoride gas; then oxidizing a silicon bromide-based deposition 44 produced during the etching step by means of oxygen radicals 46 and nitrogen radicals 47 in plasma formed from a process gas containing oxygen gas and nitrogen gas into silicon oxide; and subsequently etching the silicon oxide by means of fluorine cations 48a and fluorine radicals 48b in plasma formed from a process gas containing argon gas, and nitrogen trifluoride gas, whereby the reduction in the etching rate of a hole 43 is prevented.
摘要翻译：要解决的问题：提供一种在不降低蚀刻速率的情况下在硅层中形成具有高纵横比等的孔的基板处理方法。基板处理方法包括：通过含有氢溴酸，氧气和三氟化氮气体的工艺气体形成的等离子体中的溴阳离子45a和溴自由基45b在晶片上蚀刻多晶硅层38; 然后通过在含有氧气和氮气的工艺气体形成的等离子体中的氧自由基46和氮自由基47氧化在蚀刻步骤期间产生的基于硅溴化物的沉积物44; 随后通过含有氩气的工艺气体形成的等离子体中的氟阳离子48a和氟自由基48b以及三氟化氮气体来蚀刻氧化硅，从而防止了孔43的蚀刻速率的降低。版权所有（C）2012，JPO＆INPIT

55. 发明专利

JP2012134431A Substrate processing method and storage medium 有权
标题翻译：基板加工方法和储存介质
公开(公告)号：JP2012134431A
公开(公告)日：2012-07-12
申请号：JP2010287595
申请日：2010-12-24
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI
IPC分类号： H01L21/3065 , C23F4/00
CPC分类号： H01L21/02063 , C23F4/00 , H01J37/32091 , H01L21/02068 , H01L21/32136 , H01L21/32138 , H01L21/76805
摘要： PROBLEM TO BE SOLVED: To provide a substrate processing method which can raise an etching rate of a copper member without using a halogen gas.SOLUTION: A substrate processing apparatus 10 introduces a processing gas of a hydrogen gas added with a methane gas into an interior space of a processing chamber 15 after obtaining a Cu layer 40 having a smoothed surface 50; creates plasma from the processing gas to have oxygen radicals 52 created during etching of an oxide layer 42 and carbon radicals 53 created from methane in the inner space of the processing chamber 15; creates organic acid from the oxygen radicals 52 and the carbon radicals 53; reacts the organic acid with copper atoms of the Cu layer 40 to create a complex of the organic acid containing the copper atoms; and evaporates the created complex.
摘要翻译：要解决的问题：提供一种能够提高铜构件的蚀刻速率而不使用卤素气体的基板处理方法。解决方案：在获得具有平滑表面50的Cu层40之后，基板处理装置10将加入有甲烷气体的氢气的处理气体引入处理室15的内部空间中; 从处理气体产生等离子体以在蚀刻氧化物层42期间产生的氧自由基52和在处理室15的内部空间中由甲烷产生的碳自由基53; 从氧自由基52和碳自由基53产生有机酸; 使有机酸与Cu层40的铜原子反应，生成含有铜原子的有机酸的络合物; 并蒸发创建的复杂。版权所有（C）2012，JPO＆INPIT

56. 发明专利

JP2012054343A Fine pattern forming method 有权
标题翻译：精细图案形成方法
公开(公告)号：JP2012054343A
公开(公告)日：2012-03-15
申请号：JP2010194618
申请日：2010-08-31
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI , YAMAUCHI SHOHEI , NAKAJIMA SHIGERU , YABE KAZUO
IPC分类号： H01L21/3065 , H01L21/027 , H01L21/316 , H01L21/318 , H01L21/3213
摘要： PROBLEM TO BE SOLVED: To provide a fine pattern forming method which can suppress the inclination of a sidewall part even in the case of forming, by resist, a pattern, which makes a base for forming the sidewall part.SOLUTION: Disclosed is a fine pattern forming method comprising: an organic film forming step for forming an organic film on a layer for etching formed on a substrate; a patterning step for forming a resist film on the organic film and patterning the resist film; a deposition step for depositing a silicon oxide film to cover part of the organic film exposed from the patterned resist film, and the patterned resist film at a room temperature; a heating step for heating the substrate to cause a tensile stress in the silicon oxide film; a first etching step for etching the silicon oxide film to leave part of it on a sidewall of the patterned resist film after the heating step; and a removing step for removing the patterned resist film.
摘要翻译：要解决的问题：为了提供能够抑制侧壁部分的倾斜的精细图案形成方法，即使在通过抗蚀剂形成形成用于形成侧壁部分的基部的图案的情况下也是如此。解决方案：公开了一种精细图案形成方法，包括：在形成在基板上的蚀刻用层上形成有机膜的有机膜形成工序; 用于在有机膜上形成抗蚀剂膜并图案化抗蚀剂膜的图案化步骤; 沉积步骤，用于沉积氧化硅膜以覆盖从图案化的抗蚀剂膜暴露的部分有机膜，以及室温下图案化的抗蚀剂膜; 用于加热所述基板以在所述氧化硅膜中引起拉伸应力的加热步骤; 第一蚀刻步骤，用于在加热步骤之后蚀刻氧化硅膜以使其部分部分留在图案化的抗蚀剂膜的侧壁上; 以及去除图案化的抗蚀剂膜的去除步骤。版权所有（C）2012，JPO＆INPIT

57. 发明专利

JP2010219106A Substrate processing method 有权
标题翻译：基板处理方法
公开(公告)号：JP2010219106A
公开(公告)日：2010-09-30
申请号：JP2009061139
申请日：2009-03-13
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： KUSHIBIKI MASATO , NISHIMURA EIICHI
IPC分类号： H01L21/027 , H01L21/3065 , H01L21/316
CPC分类号： H01L21/32139 , H01J37/32082 , H01J37/32779 , H01L21/0273 , H01L21/0337
摘要： PROBLEM TO BE SOLVED: To provide a substrate processing method forming an opening having a small dimension satisfying a request for downsizing a semiconductor device on a layer to be processed.
SOLUTION: A film formation trimming step for forming a reinforced film on a photoresist film 53 as a mask layer of a wafer W, namely a substrate to be processed, and trimming line width a of a linear section for forming an opening pattern has: an adsorption step for adsorbing (a) monovalent aminosilane on the surface of the photoresist film 53; and an oxidation step for oxidizing the adsorbed aminosilane by oxygen radical where oxygen is subjected to plasma excitation, hence modifying the aminosilane to an Si oxide film, and trimming the line width (a) of the linear section of the photoresist film 53.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种形成具有小尺寸的开口的基板处理方法，其满足在要处理的层上的半导体器件的小型化的要求。＆lt; P＆gt;解决方案：一种用于在作为晶片W的掩模层的光致抗蚀剂膜53上形成增强膜的膜形成修剪步骤，即待处理的基板，以及用于形成开口图案的线性部分的修剪线宽度a 具有：在光致抗蚀剂膜53的表面上吸附（a）一价氨基硅烷的吸附步骤; 氧化步骤，其中氧气进行等离子体激发，氧化氧化吸附的氨基硅烷，由此将氨基硅烷修饰为Si氧化膜，并修整光致抗蚀剂膜53的直线部分的线宽（a）。
版权所有（C）2010，JPO＆INPIT

58. 发明专利

JP2010182730A Method of dry-etching silicon nitride film 有权
标题翻译：干蚀氮化硅薄膜的方法
公开(公告)号：JP2010182730A
公开(公告)日：2010-08-19
申请号：JP2009022611
申请日：2009-02-03
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： NISHIMURA EIICHI , SHIMIZU YUSUKE
IPC分类号： H01L21/302 , H01L21/3065
CPC分类号： H01L21/31116
摘要： PROBLEM TO BE SOLVED: To provide a method of dry-etching a silicon nitride film increasing the throughput.
SOLUTION: In the method of dry-etching the silicon nitride film 103 for dry-etching the silicon nitride film 103, the silicon nitride film 103 is dry-etched with no generation of plasma by using a process gas at least containing a hydrogen fluoride gas (HF gas) and a fluorine gas (F
2 gas) for an object to be processed 100 with the silicon nitride film 103 formed.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种干法蚀刻提高生产量的氮化硅膜的方法。解决方案：在干法蚀刻氮化硅膜103以干蚀刻氮化硅膜103的方法中，氮化硅膜103被干蚀刻，不产生等离子体，通过使用至少含有氟化氢气体（HF气体）和氟气（F 2 气体）用于形成有氮化硅膜103的待处理物体100。版权所有（C）2010，JPO＆INPIT

59. 发明专利

JP2010050376A Substrate processing method 有权
标题翻译：基板处理方法
公开(公告)号：JP2010050376A
公开(公告)日：2010-03-04
申请号：JP2008215180
申请日：2008-08-25
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： SONE TAKASHI , NISHIMURA EIICHI
IPC分类号： H01L21/3065
CPC分类号： H01L21/31144 , H01L21/0206 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/31138
摘要： PROBLEM TO BE SOLVED: To provide a substrate processing method for forming an opening, which is used for imprinting on etching objective film, on a mask film or an intermediate film while allowing the size of the opening satisfy a requirement for miniaturization of a semiconductor device with respect to a substrate to be processed.
SOLUTION: The substrate processing method for a substrate W, in which an SiN film 51, an anti-reflective film 52, a photoresist film 53 are laminated sequentially and the photoresist layer 53 includes an opening 54 for exposing part of the anti-reflective film 52, includes a shrink etching step, in which a deposit is laminated on a sidewall of an opening 54 of the photoresist film 53 by using a depository gas expressed by general formula CxHyFz (x, y, z are a positive integer), such as plasma generated from a mixed gas of CH3F gas and SF6 gas so that the opening 54 is shrunk and the anti-reflective film 52 is etched, thereby forming an opening corresponding to the shrunk opening at the anti-reflective film 52.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于在掩模膜或中间膜上形成用于刻蚀目标膜上的开口的基板处理方法，同时允许开口尺寸满足小型化的要求相对于待处理的基板的半导体器件。解决方案：依次层叠SiN膜51，抗反射膜52，光致抗蚀剂膜53的基板W的基板处理方法，光致抗蚀剂层53包括露出部分防反射膜的开口54 反射膜52包括收缩蚀刻步骤，其中通过使用由通式C x H y F z（x，y，z是正整数）表示的沉积气体将沉积物层压在光致抗蚀剂膜53的开口54的侧壁上，，例如由CH 3 F气体和SF 6气体的混合气体产生的等离子体，使得开口54收缩，并且抗反射膜52被蚀刻，从而形成对应于抗反射膜52处的收缩开口的开口。 P>版权所有（C）2010，JPO＆INPIT

60. 发明专利

JP2009111330A Substrate processing method 有权
标题翻译：基板处理方法
公开(公告)号：JP2009111330A
公开(公告)日：2009-05-21
申请号：JP2008105784
申请日：2008-04-15
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： KUSHIBIKI MASATO , NISHIMURA EIICHI
IPC分类号： H01L21/3065 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L21/31144 , H01L21/32136
摘要： PROBLEM TO BE SOLVED: To provide a substrate processing method capable of forming an opening part having dimensions satisfying a requirement to miniaturize a semiconductor device. SOLUTION: In a wafer W in which a TEOS film 51, a TiN film 52, an antireflection film 53, a photoresist film 54 are laminated on a silicon base material one by one, and the photoresist film 54 has the opening part 55 for exposing a part of the antireflection film 53, after exposing a part of the TiN film 52 by etching the exposed antireflection film 53 by plasma produced from a mixed gas of a CHF 3 gas forming a CF based deposition gas and a HBr gas forming a halogen based gas, a deposition 56 is deposited on the side face of the opening part 55 to adjust the width (DC value) of the opening part 55, and after that, etching is applied to the TiN film 52 exposed by plasma produced from a mixed gas of a Cl 2 gas and a N 2 gas. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够形成具有满足使半导体器件小型化的要求的尺寸的开口部的基板处理方法。解决方案：在其中将TEOS膜51，TiN膜52，抗反射膜53，光致抗蚀剂膜54一个接一个地层叠在硅基材上的晶片W中，并且光致抗蚀剂膜54具有开口部 55，用于暴露一部分抗反射膜53，在通过用形成CF基的CHF 3 SB气体的混合气体产生的等离子体蚀刻暴露的抗反射膜53来暴露一部分TiN膜52之后沉积气体和形成卤素气体的HBr气体，沉积56沉积在开口部分55的侧面上，以调节开口部分55的宽度（DC值），之后对TiN进行蚀刻由气体Cl 2气体和N 2 SB 2气的混合气体产生的等离子体暴露的薄膜52。版权所有（C）2009，JPO＆INPIT

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