会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 51. 发明专利
    • TRANSVERSAL FILTER
    • JPS56134821A
    • 1981-10-21
    • JP3715180
    • 1980-03-24
    • SONY CORP
    • TSUCHIYA TAKAHISASONEDA MITSUO
    • H03H15/02
    • PURPOSE:To simplify the constitution of the transversal filter of cascade connection, by dividing plural capacity components constituting a charge transfer element and by adding signal charge weighted by them and by supplying the addition signal charge to a current Miller circuit to obtain a signal current. CONSTITUTION:Suffixes of BBDa consisting of transistors (TR)Qa1-Qa5 divide even capacitors into groups Ca0' and Ca0'', and one ends of the Ca'' side are connected to terminal 6 of oscillator 8, and one ends of the Ca' side are connected mutually and are connected to TRs 11 and 12. Signal phi1' is supplied from oscillator 8 to bases of TRs 11 and 12, and the collector of TR12 is connected to current Miller circuit M1, and addition electric charge from BBDa is weighted by the filter sensibility coefficient of current Miller circuit M1, and plural signal currents are taken out from capacitor Cb5 and following points of BBDb.
    • 54. 发明专利
    • BBD
    • JPS5680888A
    • 1981-07-02
    • JP15663379
    • 1979-12-03
    • SONY CORP
    • TSUCHIYA TAKAHISASONEDA MITSUONAKAMURA ISA
    • G11C27/04G11C19/18H01L21/339H01L29/762
    • PURPOSE:To make small the relative interference and make large the dynamic range of the signal by obtaining the clock fed respectively to an electric charge controlling active element and a cold end side of memory capacity from a different generating circuit. CONSTITUTION:Bases of the transistors Q1-Q2n are separated from cold end sides of the capacitors C0-Q2n and bases of Q1, Q3,..., Q2n-1 are connected through a terminal 7a, and bases of Q2, Q4,... Q2n are connected through a terminal 6a, to a clock generating circuit 8a. The cold end sides of C1, C3,..., C2n-1 are connected through a terminal 7b, and cold end sides of C0, C2,..., C2n are connected through a terminal 6b, to a clock signal generating circuit 8b. To the output terminals 6a, 7a and 6b, 7b of the circuits 8a, 8b, clocks phi1a, phi2a and phi1b, phi2b of duty ratio 50% and reserve polarity are respectively output and an input signal of the terminal 1 synchronizes with these clocks and moves.