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2. 发明专利

JP2001344559A ANALOG MULTIPLYING CIRCUIT AND VARIABLE GAIN AMPLIFIER CIRCUIT 失效
公开(公告)号：JP2001344559A
公开(公告)日：2001-12-14
申请号：JP2000160841
申请日：2000-05-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： AMANO YASUHIRO
IPC分类号： G06G7/163 , H03G3/10
摘要： PROBLEM TO BE SOLVED: To enable an analog multiplying circuit to perform highly linear operation with

3. 发明专利

JP3171137B2 失效
公开(公告)号：JP3171137B2
公开(公告)日：2001-05-28
申请号：JP11041197
申请日：1997-04-11
IPC分类号： G06G7/163 , H03F3/45 , H03G11/08

4. 发明专利

JP2001076083A ANALOG MULTIPLIER 失效
公开(公告)号：JP2001076083A
公开(公告)日：2001-03-23
申请号：JP25137699
申请日：1999-09-06
申请人： JAPAN RADIO CO LTD
发明人： ADACHI MASAYUKI
IPC分类号： G06G7/163 , H03D7/00
摘要： PROBLEM TO BE SOLVED: To obtain an analog multiplier which can actualize the temperature compensation of a gain, even at a low source voltage. SOLUTION: An analog multiplier 200 is equipped with a reference voltage generating circuit 22, a voltage-converting circuit 26, and a constant-current supply part 24. The reference voltage generating circuit 22 is capable of outputting reference voltage Vref, having an arbitrary temperature coefficient. The voltage converting circuit 26, while maintaining the temperature coefficient generated by the reference voltage generating circuit 22, is capable of converting the reference voltage Vref into an arbitrary reference voltage Vb. An analog multiplier, having a low source voltage, has its gain compensated for temperature by setting the reference voltage Vb and temperature coefficient, according to the linear input range of the analog multiplier.

5. 发明专利

JP3127952B2 失效
公开(公告)号：JP3127952B2
公开(公告)日：2001-01-29
申请号：JP19585296
申请日：1996-07-25
IPC分类号： G06G7/163

6. 发明专利

JP2000251007A MOS MULTIPLICATION CIRCUIT 失效
公开(公告)号：JP2000251007A
公开(公告)日：2000-09-14
申请号：JP5013899
申请日：1999-02-26
申请人： NEC CORP
发明人： KIMURA KATSUHARU
IPC分类号： G06G7/163
摘要： PROBLEM TO BE SOLVED: To provide an MOS multiplication circuit which can be formed on a semiconductor integrated circuit. SOLUTION: The sources of first to fourth transistors, for which a constant voltage is impressed between a gate and a source, are connected in common, first to fourth differential transistors composed of transistors M5-M12, the sources of which are connected in common and the drains of which are also connected in common, are connected to the drains of transistors M1-M4 while being driven by a ground or constant current source and when first and second input voltages are defined as V1 and V2, V3 is defined as an arbitrary voltage and (a), (b) and (c) are defined as arbitrary constants, voltages aV1+V3, bV2+V3, (a-c)V1+V3, (b-1/c)V2+V3, (a-c)V1+V3, bV2+V3, aV1+V3 and (b-1/c)V2+V3 are respectively impressed to the gates of the transistors M5-M12. Then, a differential current between the sum current of output currents from the first and second differential transistors and the sum current of output currents from the third and fourth transistors is defined as an output current and a current proportional to the product of first and second input voltages is outputted.

7. 发明专利

JP3062999B2 失效
公开(公告)号：JP3062999B2
公开(公告)日：2000-07-12
申请号：JP15771398
申请日：1998-06-05
IPC分类号： G06G7/163 , H03F3/45 , H03G3/10

8. 发明专利

JP2000076371A Mos multiplier circuit 审中-公开
标题翻译： MOS MULTIPLIER电路
公开(公告)号：JP2000076371A
公开(公告)日：2000-03-14
申请号：JP24274298
申请日：1998-08-28
申请人： Nec Corp , 日本電気株式会社
发明人： KIMURA KATSUHARU
IPC分类号： G06G7/163 , H03D7/12 , H03D7/14
摘要： PROBLEM TO BE SOLVED: To provide a MOS multiplier circuit of a comparatively small circuit scale by providing a multiplier core circuit commonly connecting the drains of respective first/second transistors so as to constitute one output terminal and commonly connecting the drains of respective third/fourth transistors so as to constitute the other output terminal. SOLUTION: The circuit is provided with MOS transistors M1 and M2 forming a first multiplier circuit, where sources are grounded and V1+v1, V2+v2 are applied to gates and drains commonly connected and connected with a power source through a resistor R. Similarly the circuit is provided with MOS transistors M3, M4 forming a second multiplier circuit applied with V1-v1, V2-v2, MOS transistors M5, M6 forming a third multiplier circuit applied with V1+v1, V2-v2 and MOS transistors M7, M8 forming a fourth multiplier circuit applied with V1-v1, V2+v2. A dynamic range in outputting is secured by providing a multiplier core circuit constituted like this.
摘要翻译：要解决的问题：通过提供一个通用连接各个第一/第二晶体管的漏极的乘法器芯电路来提供比较小的电路规模的MOS倍增器电路，从而构成一个输出端子，并且共同连接相应的第三/第四晶体管的漏极晶体管构成另一输出端。解决方案：电路设有形成第一乘法器电路的MOS晶体管M1和M2，其中源极接地，并且V1 + v1，V2 + v2施加到通过电阻R共同连接并与电源连接的栅极和漏极。类似地电路设置有形成施加有V1-v1，V2-v2的第二乘法器电路的MOS晶体管M3，M4，形成施加有V1 + v1，V2-v2和MOS晶体管M7，M8的第三乘法电路的MOS晶体管M5，M6 形成应用V1-v1，V2 + v2的第四乘法器电路。通过提供如此构成的乘法器核心电路来确保输出中的动态范围。

9. 发明专利

JP2000057242A 4TH QUADRANT MULTIPLICATION CIRCUIT 失效
公开(公告)号：JP2000057242A
公开(公告)日：2000-02-25
申请号：JP22973898
申请日：1998-08-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： TAKEUCHI TAKANOBU
IPC分类号： G06G7/163
摘要： PROBLEM TO BE SOLVED: To permit driving by low voltage by making a 1st voltage compression circuit constructed with P channel MOSFET and making a 2nd voltage compression circuit constructed with an N channel MOSFET. SOLUTION: A P channel voltage compression circuit 101 steps down input voltage Vin (a) and reference voltage Vref 1 in a prescribed ratio and outputs them. An N channel voltage compression circuit 102 steps down input voltage Vin (b) and the reference voltage Vref 1 in a prescribed ratio. It is possible to apply voltage that is higher than the voltage Vref 1 to the gate voltage of PMOSs 40 to 43 of a current conversion circuit 106 and to apply voltage that is lower than the voltage Vref 1 to the gate voltage of PMOSs 20 to 23 of 1st and 2nd voltage conversion circuits 103 and 104. Thus, it is possible to operate the PMOSs 20 to 23 in a pentode area even if power supply voltage Vcc is low.

10. 发明专利

JPH11355075A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH11355075A
公开(公告)日：1999-12-24
申请号：JP15771398
申请日：1998-06-05
申请人： SEIKO INSTR INC
发明人： YAMAMOTO YUJI
IPC分类号： G06G7/163 , H03F3/45 , H03G3/10
摘要： PROBLEM TO BE SOLVED: To provide an amplifier circuit with less fluctuation in gain and the gain of which is inversely proportionated to the gain control current. SOLUTION: The amplifier circuits consisting of a differential input stage MDn and a load stage MLn are serially connected at two stages. The gain is controlled by controlling current to be supplied to load transistors ML1, ML2, ML3, ML4 and changing the gm at a load stage. The fluctuation in the gain is less since the gain is set in a ratio of the gm as differential input stage gm/load stage gm. The current is inversely proportional to √ current in the amplifier circuit at one stage, however, the gain is made proportional to the current by serially connecting the amplifier circuits at two stages.

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