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51. 发明专利

JPH02112274A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH02112274A
公开(公告)日：1990-04-24
申请号：JP26394588
申请日：1988-10-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIZAKI TAKESHI , MURANAKA MASAYA
IPC分类号： G11C11/401 , H01L21/822 , H01L27/02 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108
摘要： PURPOSE:To make effective a layout by disposing a substrate back-bias voltage generator circuit at the center of a plurality of memory arrays disposed symmetrically on a semiconductor substrate, and providing a predetermined distance between the substrate back-bias voltage generator circuit and each memory array. CONSTITUTION:In a dynamic type RAM, a substrate back-bias voltage generator circuit VBBG disposed at the center of a semiconductor substrate SUB is separated by an about 600-700mum distance d from memory arrays RARY0, MARY2. The substrate back-bias voltage generator circuit VBBG is disposed at the center of the semiconductor substrate SUB together with a peripheral circuit PC that requires a relatively large layout area in such a manner, so that an insignificant space is eliminated and there can be defined the predetermined distance d enough to ignore the amount of minority carriers injected from the substrate back-bias voltage generator circuit VBBG into a memory cell, between the substrate back-bias voltage generator circuit VBBG and each memory array. Hereby, the layout of a dynamic type RAM is made effective with the low cost of manufacture thereof.

52. 发明专利

JPH0286157A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0286157A
公开(公告)日：1990-03-27
申请号：JP23642888
申请日：1988-09-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI YASUSHI , MIYAZAWA KAZUYUKI , IWAI HIDETOSHI , MURANAKA MASAYA
IPC分类号： H01L23/50
摘要： PURPOSE:To correspond with a different kind of package by using the same semiconductor chip by a method wherein a bonding pad to be used is selected according to the kind of package, and a lead frame according to each package is used. CONSTITUTION:For example, an insulating sheet 4 is bonded on a retaining plate 3 and the inner lead parts of lead L4, L11, L12, and a semiconductor chip 1 of 4MDRAM is mounted on the insulating sheet 4. The lead frame is formed of copper alloy or iron nickel alloy, and the insulating sheet 4 of polyimide resin and the semiconductor chip 1 are mounted, by using adhesive agent or by compression bonding. Bonding parts of leads L1-L3, L11-L20 and the bonding pads P1-P3, P8, P9-P13, P20-P30 on a semiconductor chip are connected electrically by using bonding wires W. When this wire bonding is finished, a resin seal type semiconductor device is completed by a resin seal process, In this case, epoxy resin is used as sealing resin.

53. 发明专利

JPH0258377A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0258377A
公开(公告)日：1990-02-27
申请号：JP20843288
申请日：1988-08-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI YASUSHI , MATSUURA NOBUMI , KOYAMA YOSHIHISA , MURANAKA MASAYA , KIMURA KATSUTAKA , IWAI HIDETOSHI , MIYAZAWA KAZUYUKI , ISHIHARA MASAMICHI
IPC分类号： H01L23/522 , G11C11/401 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To realize high speed advancement of operation speed of a semiconductor integrated circuit device having DRAM by making wiring layers at the first and second layers into the wiring layers for signal transmission which are connected electrically at every specified interval. CONSTITUTION:In DRAM1, standard clock signal generating circuits (RAS and/or CAS) which are arranged respectively on opposite short sides of a rectangular chip and address circuits (XAB, YAB) are provided extendedly along the long side of the rectangular chip and are connected with standard clock signal wires in short-circuited two-layer wiring structure. Hereby, the resistance value of the standard clock signal wiring is reduced as compared with the case of single layer wiring structure, and high speed advancement of the transmission speed of standard clock signals is achieved. Hereby, the margin of address set-up time and address hold time improves, and high speed advancement of the operation speed of the DRAM1 can be achieved.

54. 发明专利

JPS6481358A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6481358A
公开(公告)日：1989-03-27
申请号：JP23724387
申请日：1987-09-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA , MURATA JUN , MORIUCHI NOBORU , SEKIGUCHI TOSHIHIRO
IPC分类号： H01L27/04 , H01L21/3205 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To accurately form a power supply contact hole with an excellent accuracy by providing a dummy pattern made of a first layer polycrystalline silicon film under a contact part of a third layer polycrystalline silicon film and wirings for supplying power to the third layer film. CONSTITUTION:In a semiconductor integrated circuit device having a stacked capacitor type memory cell, a dummy pattern DP1 made of a first layer polycrystalline silicon film is provided on the field insulating film 2 of the memory cell. Since the pattern DP1 is provided under the contact with wirings for supplying power to a third layer polycrystalline silicon film 9 for forming one electrode of a stacked capacitor, the step of the surface of a photoresist 10 can be alleviated above the contact in the amount corresponding to the thickness, and the thickness becomes more uniform. Thus, the margin of focusing in case of exposing the photoresist is increased, and a contact hole 6b can be accurately formed without irregularity in the diameter of the hole.

55. 发明专利

JPS6480041A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6480041A
公开(公告)日：1989-03-24
申请号：JP23590187
申请日：1987-09-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI YASUSHI , MATSUURA NOBUMI , KOYAMA YOSHIHISA , MURANAKA MASAYA , KIMURA MASATAKA , MIYAZAWA KAZUYUKI , ISHIHARA MASAMICHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To prevent the disconnection of aluminum wiring at the second layer in a part which is stepped because of aluminum wiring at the first layer, by causing the thickness of aluminum wiring at the first layer to be thinner than that of aluminum wiring at the second layer. CONSTITUTION:Aluminum wiring Al 1 at the first layer is mounted on a layer insulation film 3 and aluminum wiring Al 2 at the second layer is mounted on the layer insulation film 4. In such a case, this device allows the thickness of wiring Al 1 to be thinner than that of wiring of Al 2. Then, a stepped part which is caused by wiring Al 1 at the base surface of wiring Al 2 becomes small. Thus, this situation serves the purpose of improving the step coverage of wiring Al 2 at the stepped part and accordingly, preventing the disconnection of wiring Al 2 at the stepped part.

56. 发明专利

JPS6452291A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6452291A
公开(公告)日：1989-02-28
申请号：JP20814487
申请日：1987-08-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA
IPC分类号： G11C11/409 , G11C11/34 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To improve an access speed and to attain a high density by cutting or connecting, through a high resistance, the middle of the shorter line of a current channel flowing at the time of reading in a memory, which adopts a twisted common drive line sense amplifier. CONSTITUTION:The layout of a sense amplifier SAU in an upper array ARYU and a sense amplifier SAD in a lower array ARYD are mutually constituted in the reverse direction. When the SAUs in the ARYU are all activated, the current flows from a common drive-line CDL 2 through the SAU to a CDL 1. Next, when the SAU is turned off, and the SAD is activated, the current flow from the CDL 1 through the SAD to the CDL 2. Consequently, the channel of the CDL 1 where the current flows is longer, and the current does not flow to the CDL 2 and CDL 2' simultaneously. For this reason, by connecting the CDL 2 with the CDL 2' with the high resistance, a driving time constant can be minimized, and the access speed is improved.

57. 发明专利

JPS63292500A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63292500A
公开(公告)日：1988-11-29
申请号：JP12942487
申请日：1987-05-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA , TAKAHASHI YASUSHI
IPC分类号： H01L21/82 , G11C11/34 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/822 , H01L27/04 , H01L27/10
摘要： PURPOSE:To reduce an exclusive area of a redundant circuit, and to improve the yield by forming a switching signal to a stand-by memory line or row by a programmable logic having a programming element. CONSTITUTION:In a programmable logic 5, at every unit address buffer AB0-ABi for constituting an address buffer circuit 1, each pair of fuses F01, F02-Fi1, Fi2 is provided in accordance with internal address signals a0, the inverse of a0-ai, and the inverse of ai being its output signals, one end of each pair of fuses is connected to an output terminal of the address buffer, and the other end is connected in common. This common connecting terminal is connected to one of input terminals of a multi-input NAND circuit 6, and one of each pair of fuses F01-Fi2 is connected by a laser, therefore, one of a true or false level is sent to the circuit 6. Accordingly, only when it has been decided that an address of each pair is a failure, in accordance with a failure address detected by a probe inspection, all inputs of the circuit 6 are set to a high level by cutting one fuse.

58. 发明专利

JPS63142591A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63142591A
公开(公告)日：1988-06-14
申请号：JP28885486
申请日：1986-12-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA , YOSHIDA MASAHIRO , KUBONO SHIYOUJI
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE:To attain simplified picture system and low cost by providing a row address generating circuit in a dual port memory thereby having only to supply a serial clock signal externally. CONSTITUTION:A final row address signal supplied externally via a row address buffer RADB is inputted to an address detection circuit RAD via a row address register RAR of a row address generating circuit RAG. Moreover, a row address counter RAC supplies a data transfer row address signal advanced at each data transfer cycle to an address multiplexer AMX and supplies it to the circuit RAD. The circuit RAD compares signals from the counter RAC and the register RAR and when they are coincident, a final address signal syn is sent to a timing control circuit TC via an AND gate circuit AG. Thus, the word line within the designated range is designated sequentially to continue the input/output operation thereby attaining simplicity and low cost.

59. 发明专利

JPS6379296A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6379296A
公开(公告)日：1988-04-09
申请号：JP22357286
申请日：1986-09-24
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： MURANAKA MASAYA , YOSHIDA MASAHIRO
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE:To attain multi-functioned device without extension of external terminals by applying prescribed combination to control signals supplied externally and executing one mode of a semiconductor storage device depending on its start cycle and plural succeeding start cycles. CONSTITUTION:It is decided that a control signal supplied externally is a dummy cycle being prescribed combination of signals and the succeeding input signal is inputted as a signal having a different meaning from a normal cycle. In this case, the control signal for dummy cycle consists of a law address strobe signal RAS a column address strobe signal CAS and a write enable signal WE, a decision circuit uses the signals CAS, WE being at a low level before the signal RAS goes to a low level to identify the dummy cycle. Then the prescribed function code is inputted/outputted succeedingly. Thus, the dual port memory is provided with a function control circuit, a logic arithmetic circuit, a decoder and a selector.

60. 发明专利

JPS6354014A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6354014A
公开(公告)日：1988-03-08
申请号：JP19717386
申请日：1986-08-25
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： MURANAKA MASAYA , OKAYAMA OSAMU , MATSUURA HIROMI , KEMISAKI KANEHIDE
IPC分类号： H03K5/1252 , G11C11/34 , G11C11/407 , G11C11/409 , H03K5/00
摘要： PURPOSE:To prevent malfunction of a dynamic RAM or the like by using a delay control signal so as to control a level control circuit comprising series MODFETs thereby bringing the signal to a threshold value after a delay time resulting in eliminating noise within the delay time. CONSTITUTION:A control signal such as a low strobe signal, inverse of RAS, changes to an H level, then an output of a CMOS inverter N1 of a iming control circuit TC goes to an intermediate level not reaching the threshold value of an inverter N4. On the other hand, the signal. inverse of RAS via the delay circuit DL turns on FETs Q7, Q6 among PMOSFETs Q2, Q3 and NMOSFETs Q6, Q7 connected in sereis between a power supply Vcc and ground of a level control circuit LV, a latched signal L is fed to the circuit, LV, the input of the CMOS inverter N4 reaches a threshold value, and after the delay time elapses, an internal low strobe signal, the inverse of RAS of an H level is outputted without being effected by a noise of a minute time width of the signal, the inverse of RAS within the delay time. Similarly, when the signal, the inverse of RAS changes to L, malfunction of the dynamic RAM or the like due to minute noise is prevented.

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