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51. 发明专利

JPH0485948A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0485948A
公开(公告)日：1992-03-18
申请号：JP20084990
申请日：1990-07-27
申请人： HITACHI LTD
发明人： OGISHIMA JUNJI , SUWAUCHI NAOKATSU , UCHIYAMA HIROYUKI
IPC分类号： H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To avoid defective cutting of a redundant fuse element by a method wherein the redundant fuse element is composed of the same conductor layer as the plate electrode of the stacked structure information storing capacitance element of a memory cell to which a fixed potential is applied. CONSTITUTION:A semiconductor integrated circuit device has a DRAM composed of a memory cell M which is composed of a series circuit of a memory cell selecting MIS-FET Qs and a stacked structure information storing capacitance element C and a redundant fuse element F, which is cut by a laser cutting method, of a redundant circuit which helps the memory cell. The redundant fuse element F is composed of the same conductive layer as the plate electrode 14 of the stacked structure information storing capacitance element C of the memory cell M to which a fixed potential is applied. With this constitution, the plate electrode 14 of the stacked structure information storing capacitance element C of the memory cell M is made of the mate material of an uppermost layer in a DRAM manufacturing process and the redundant fuse element F can be isolated from the main surface of a p--type semiconductor substrate 1, so that the defective cutting of the redundant fuse care be avoided and, further, damages against the semiconductor substrate side can be suppressed.

52. 发明专利

JP2013214537A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013214537A
公开(公告)日：2013-10-17
申请号：JP2010147966
申请日：2010-06-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： FUJII KUNIHARU , UCHIYAMA HIROYUKI , WAKANA HIRONORI , KAWAMURA TETSUSHI
IPC分类号： H01L29/786 , H01L21/28 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/417
CPC分类号： H01L29/7869 , H01L29/45
摘要： PROBLEM TO BE SOLVED: To provide a technology of enabling inhibition of characteristic deterioration of a thin film transistor in a semiconductor device including the thin film transistor which uses a metal oxide semiconductor film for a channel layer, particularly in a semiconductor device having a heat history after formation of the above-described thin film transistor.SOLUTION: A semiconductor device comprises a source electrode SE and a drain electrode DE which include a first electrode layer FE composed of a metal film such as aluminum (Al), silver (Ag), gold (Au) and copper (Cu), and a diffusion prevention layer DC which is formed between a channel layer CH and the first electrode layer FE so as to contact the channel layer CH in order to prevent the metal composing the first electrode layer FE from diffusing to the channel layer CH, and which is composed of a cobalt film.
摘要翻译：要解决的问题：提供一种能够抑制包括使用用于沟道层的金属氧化物半导体膜的薄膜晶体管的半导体器件中的薄膜晶体管的特性劣化的技术，特别是在具有热历史的半导体器件中在形成上述薄膜晶体管之后。半导体器件包括源电极SE和漏电极DE，其包括由诸如铝（Al），银（Ag）等金属膜构成的第一电极层FE，金（Au）和铜（Cu），以及扩散防止层DC，其形成在沟道层CH和第一电极层FE之间以与沟道层CH接触以防止构成第一电极层FE的金属从扩散到沟道层CH，并且由钴膜组成。

53. 发明专利

JP2013149833A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013149833A
公开(公告)日：2013-08-01
申请号：JP2012010000
申请日：2012-01-20
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： WAKANA HIRONORI , UCHIYAMA HIROYUKI , KAWAMURA TETSUSHI , OZAKI HIROAKI , YAMAZOE TAKANORI
IPC分类号： H01L21/822 , G06K19/07 , G06K19/077 , H01L27/04 , H01L29/786 , H01Q1/38 , H01Q1/40
CPC分类号： H01Q1/2208 , H01L27/1225 , H01L27/1255 , H01Q1/38 , H01Q1/40 , H01Q7/00
摘要： PROBLEM TO BE SOLVED: To improve a performance of a semiconductor device.SOLUTION: In a semiconductor device in which an IC part and a coil antenna connected to the IC part are formed on the same substrate, the coil antenna is formed by conductive layers ANT1, ANT2 which are layers different from each other. Between the conductive layers ANT1, ANT2, an interlayer insulation film is sandwiched. The conductive layers ANT1, ANT2 have overlapping parts OVL at each of which the conductive layers ANT1, ANT2 overlap each other via the interlayer insulation film in a direction perpendicular to a principal surface of a substrate. Each of the conductive layer ANT1 and the conductive layer ANT2 has a width narrower at the overlapping part OVL than at another part.
摘要翻译：要解决的问题：提高半导体器件的性能。解决方案：在与IC部分连接的IC部分和线圈天线形成在同一基板上的半导体器件中，线圈天线由导电层ANT1 ，ANT2是彼此不同的层。在导电层ANT1，ANT2之间夹有层间绝缘膜。导电层ANT1，ANT2具有重叠部分OVL，其中每个导电层ANT1，ANT2在垂直于衬底主表面的方向上经由层间绝缘膜彼此重叠。导电层ANT1和导电层ANT2中的每一个在重叠部分OVL处的宽度比在另一部分处的宽度窄。

54. 发明专利

JP2011054812A Thin film transistor, and method for manufacturing the same 审中-公开
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：JP2011054812A
公开(公告)日：2011-03-17
申请号：JP2009203274
申请日：2009-09-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KAWAMURA TETSUSHI , UCHIYAMA HIROYUKI , WAKANA HIRONORI , HATANO MUTSUKO
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7869 , H01L29/66969 , H01L29/78696
摘要： PROBLEM TO BE SOLVED: To suppress increase of dispersion of a TFT characteristic in forming a top contact type TFT using dry etching for processing of a source-drain electrode, degradation of a yield, and reduction in a TFT on-current. SOLUTION: In this manufacturing method for a thin-film transistor, a sacrifice layer formed of a metal oxide semiconductor is formed over a conductive layer formed of a metal oxide semiconductor; a metal film is formed over the sacrifice layer; the metal film is processed by dry etching; and the sacrifice layer exposed by the dry etching is subjected to wet etching. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了抑制用于处理源极 - 漏极电极的干法蚀刻形成顶部接触型TFT的TFT特性的分散增加，产率降低和TFT导通电流的降低。解决方案：在这种薄膜晶体管的制造方法中，在由金属氧化物半导体形成的导电层上形成由金属氧化物半导体形成的牺牲层; 在牺牲层上形成金属膜; 金属膜通过干蚀刻加工; 通过干蚀刻曝光的牺牲层进行湿蚀刻。版权所有（C）2011，JPO＆INPIT

55. 发明专利

JP2011044575A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011044575A
公开(公告)日：2011-03-03
申请号：JP2009191589
申请日：2009-08-21
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KAWAMURA TETSUSHI , UCHIYAMA HIROYUKI , WAKANA HIRONORI , HATANO MUTSUKO , SATO TAKESHI
IPC分类号： H01L29/786 , G02F1/1368 , H01L21/28 , H01L21/336
CPC分类号： H01L29/7869
摘要： PROBLEM TO BE SOLVED: To actualize a self-alignment process free of trouble during use of a liftoff and so on for an oxide semiconductor since a self-alignment process employing an ion implantation method like a bulk silicon MOS transistor and a polycrystalline silicon TFT can not be incorporated because it is difficult for the oxide semiconductor to form a diffusion layer by the ion implantation method. SOLUTION: A thin-film transistor (TFT) manufactured by back surface exposure uses the oxide semiconductor as a channel layer, negative resist on a conductive film is exposed from a back surface side of a substrate using an electrode on the substrate as a mask, and then removed except an exposed part of the negative resist, and the conductive film is etched using the exposed part as an etching mask to process the electrode. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了实现在氧化物半导体的剥离等的使用过程中没有麻烦的自对准过程，因为使用诸如体硅MOS晶体管和多晶硅的离子注入方法的自对准过程由于通过离子注入方法难以使氧化物半导体形成扩散层，所以不能并入硅TFT。解决方案：通过背面曝光制造的薄膜晶体管（TFT）使用氧化物半导体作为沟道层，使用基板上的电极从基板的背面侧露出导电膜上的负性抗蚀剂，掩模，然后除去负抗蚀剂的暴露部分，并且使用暴露部分作为蚀刻掩模蚀刻导电膜以处理电极。版权所有（C）2011，JPO＆INPIT

56. 发明专利

JP2006071300A Biochemical substance detector 审中-公开
标题翻译：生物化学物质检测器
公开(公告)号：JP2006071300A
公开(公告)日：2006-03-16
申请号：JP2004251516
申请日：2004-08-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SHIRAI MASATAKA , SUGAWARA TOSHIKI , UCHIYAMA HIROYUKI , UEMATSU CHIHIRO
IPC分类号： G01N21/27 , C12M1/34 , G01N33/53 , G01N33/543
CPC分类号： G01N21/554 , G01N33/54373
摘要： PROBLEM TO BE SOLVED: To solve the problem that measurement is simple and rapid in a biochemical sensor not using a label such as a phosphor or the like because the introduction of the label into a sample is unnecessary but a conventional non-labelled sensor is insufficient in sensitivity as compared with a measuring method using the label and measuring precision is deteriorated in a sample insufficient in refining. SOLUTION: The molecule selectively bonded to the substance desired to be detected in the sample is vibrated and a change in the vibration states before and after bonding is measured to measure the amount of the molecule desired to be detected. By this method, the effect of impurities different in vibration state can be suppressed. Further, by subjecting the cyclic signal due to molecular vibration to lock-in measurement, the 1/f noise caused by the adsorption and dissociation of the molecule on the surface of a solid is reduced to enhance sensitivity. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决问题：为了解决在不使用荧光体等标签的生物化学传感器中测量简单快速的问题，因为将标记引入样品是不必要的，但是常规的未标记传感器与使用标签的测量方法相比灵敏度不足，并且在精炼不充分的样品中测量精度降低。解决方案：选择性地键合到期望在样品中检测的物质的分子被振动，并测量粘合前后的振动状态的变化，以测量期望被检测的分子的量。通过该方法，能够抑制振动状态下的杂质的影响。此外，通过使由于分子振动引起的循环信号进行锁定测量，减少了由固体表面上的分子的吸附和解离引起的1 / f噪声，以提高灵敏度。版权所有（C）2006，JPO＆NCIPI

57. 发明专利

JP2005142982A High-frequency mems switch and its manufacturing method 有权
标题翻译：高频MEMS开关及其制造方法
公开(公告)号：JP2005142982A
公开(公告)日：2005-06-02
申请号：JP2003379390
申请日：2003-11-10
申请人： Hitachi Ltd , Hitachi Media Electoronics Co Ltd , 株式会社日立メディアエレクトロニクス , 株式会社日立製作所
发明人： ISOBE ATSUSHI , TERANO AKIHISA , ASAI KENGO , UCHIYAMA HIROYUKI , MATSUMOTO HISAKATSU
IPC分类号： B81B3/00 , B81C1/00 , H01H1/20 , H01H59/00 , H01P1/12
CPC分类号： H01H59/0009 , H01H1/20 , H01P1/127
摘要： PROBLEM TO BE SOLVED: To provide an inexpensive MEMS switch that stably operates with a low voltage, and its manufacturing method.
SOLUTION: The high-frequency MEMS switch comprises a first anchor 7-2-1 formed on a substrate 3, a first spring 7-3-1 connected to the first anchor, an upper electrode 7-1 that is connected to the first spring and applies elastic deformation to the first spring to move above the substrate 3, a lower electrode 1 formed on the substrate located under the upper electrode, a second spring 7-3-2 connected to the upper electrode, and a second anchor 7-2-2 connected to the second spring. When a voltage is applied between the upper electrode and the lower electrode to move the upper electrode downwards, the second anchor comes into contact with the substrate, the second spring elastically deforms and the upper electrode then comes into contact with the lower electrode, so that the upper electrode and the second electrode are electrically connected. The first and second anchors, the first and second springs and the upper electrode are integrally manufactured from the same metal and become a membrane 7.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种以低电压稳定运行的便宜的MEMS开关及其制造方法。解决方案：高频MEMS开关包括形成在基板3上的第一锚7-2-1，连接到第一锚的第一弹簧7-3-1，与第一锚7相连的上电极7-1 第一弹簧并且对第一弹簧施加弹性变形以在基板3上方移动，形成在位于上电极下方的基板上的下电极1，连接到上电极的第二弹簧7-3-2和第二锚 7-2-2连接到第二弹簧。当在上部电极和下部电极之间施加电压以向上移动上部电极时，第二锚定器与基板接触，第二弹簧弹性变形，并且上部电极随后与下部电极接触，使得上电极和第二电极电连接。第一和第二锚，第一和第二弹簧和上电极由相同的金属一体制造并成为膜7.版权所有（C）2005，JPO＆NCIPI

58. 发明专利

JP2003007706A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2003007706A
公开(公告)日：2003-01-10
申请号：JP2001194078
申请日：2001-06-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UCHIYAMA HIROYUKI , SHIODA TAKASHI
IPC分类号： G03F7/038 , G03F7/40 , H01L21/28 , H01L21/288 , H01L21/308 , H01L21/3205 , H01L21/331 , H01L21/335 , H01L21/768 , H01L21/8252 , H01L23/52 , H01L27/06 , H01L27/095 , H01L29/737
CPC分类号： H01L29/66318 , H01L21/3081 , H01L21/76898 , H01L21/8252 , H01L27/0605 , H01L29/66462
摘要： PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device for using a mask material that has excellent dry etching resistance and can be formed at low temperature to achieve a fine via hole and a high yield in a semiconductor via hole-machining process, and achieving a high-performance ultra-high-frequency semiconductor device. SOLUTION: A light-sensitive polyimide resin is used as a mask for etching machining. In the light-sensitive polyimide, a mask process due to a projection aligner can be made as in resist, and film thickness formation of 10 to 40 μm can also be made easily. Etching resistance is excellent, and by vitrifying it through curing treatment at a relatively low temperature of 200 to 250 deg.C, the selectivity ratio can be improved up to approximately 20.
摘要翻译：要解决的问题：为了提供使用具有优异的耐干蚀刻性的掩模材料的半导体器件的制造方法，并且可以在低温下形成以在半导体通孔加工过程中实现细通孔和高产率，并实现了高性能超高频半导体器件。解决方案：使用光敏聚酰亚胺树脂作为蚀刻加工的掩模。在光敏聚酰亚胺中，可以制成由于投影对准器而形成的掩模工艺，如抗蚀剂，并且也可以容易地形成10μm至40μm的膜厚度。耐蚀性优异，通过在200〜250℃的较低温度下进行固化处理使其玻璃化，可以使选择比提高至20左右。

59. 发明专利

JP2001267287A MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001267287A
公开(公告)日：2001-09-28
申请号：JP2000077806
申请日：2000-03-15
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： UCHIYAMA HIROYUKI , SHIODA TAKASHI , OTA HIROSHI
IPC分类号： H01L29/73 , H01L21/306 , H01L21/331 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of semiconductor device for realizing anisotropic (selective) etching of a compound semiconductor element with hetero structure through wet etching and carrying out anisotropic processing with highly controllable and highly uniform comparable to that of a dry etching. SOLUTION: Composition of an etching liquid as well as an etching temperature are important for realizing anisotropic etching through wet etching. The etching liquid is prepared by mixing an organic acid containing at least ascorbic acid, hydrogen peroxide, water, and a pH moderator for example ammonia. The etching temperature is controlled at a specific temperature. In a selective anisotropic etching step of GaAs with an etching stopping layer of AlGaAs, the anistropic etching with the controllability in dimensions almost equal to a conventional dry etching can be obtained when the etching temperature is made under control at 10 deg.C or below. Furthermore, since an isotropic etching can be performed by control of the temperature to 10 deg.C and over, processing for complicated shapes can be carried out easily under control of only temperature.

60. 发明专利

JP2001250926A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001250926A
公开(公告)日：2001-09-14
申请号：JP2000058354
申请日：2000-03-03
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , OGISHIMA JUNJI , UCHIYAMA HIROYUKI
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a technology for obtaining a desired threshold voltage of a MISFET for memory cell selection, and at the same time for suppressing the deterioration of refresh characteristics by specifying the shape of the active region of a memory cell. SOLUTION: The shape of an active region (b) is set to a diamond shape with a round corner, and an active width Lb of a gate end at the bit-line side of the MISFET for memory cell selection is set to approximately 2 to 3 times larger than the minimum machining dimensions, thus decreasing the influence of boron segregation to an insulating film for composing an element separation region (a). On the other hand, active width Lc of the gate end at the side of a capacitor for information accumulation of the MISFET for memory cell selection is set narrower than the minimum machining dimensions, thus increasing the influence of the boron segregation to the insulating film for composing the element separation region (a).

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