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51. 发明专利

JPH08186376A HIGH-DENSITY THIN FILM MALTILAYER WIRING BOARD, MOUNTING STRUCTURE THEREOF, AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08186376A
公开(公告)日：1996-07-16
申请号：JP32660694
申请日：1994-12-28
申请人： HITACHI LTD
发明人： YAMAZAKI TETSUYA , ISHINO MASAKAZU , SHOJI FUSAJI , TOGAWA HIDEO , KYOI MASAYUKI
IPC分类号： C09J7/02 , C09J5/06 , H05K3/38 , H05K3/46
摘要： PURPOSE: To manufacture a high-density thin film multilayer wiring board such as a multi-chip module at a low cost keeping it high wiring density without deteriorating it in transmission rate by a method wherein organic resin film structures each specified in thickness and relative dielectric constant are laminated. CONSTITUTION: A polyimide film 2 is formed on a copper foil 1. Then, a wiring pattern 3 of film resist is formed on the copper foil 1. The copper foil 1 is etched through the wiring pattern 3 of film resist as a mask for the formation of the polyimide film 2 provided with a wiring pattern 4. Then, an adhesive layer 5 of thickness 10 to 30μm and relative dielectric constant 2.2 to 4.0 is formed on the side of the polyimide film 2 where no wiring pattern 4 is provided. By this setup, a polyimide film structure 15 composed of the polyimide film 2 provided with a wiring pattern 4 on its front side and the adhesive layer 5 on its rear side is formed. Then, the polyimide film structures 15 are aligned with each other and laminated by the use of the guide pins 7 of a jig 6 and guide holes 8 bored in the polyimide structures 15.

52. 发明专利

JPH07283280A CONNECTING DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07283280A
公开(公告)日：1995-10-27
申请号：JP2689595
申请日：1995-02-15
申请人： HITACHI LTD
发明人： KASUKABE SUSUMU , USAMI MITSUO , UEHARA KEIJIRO , TASE TAKASHI , ISHINO MASAKAZU , KASHIMURA TAKASHI
IPC分类号： G01R31/26 , G01R1/073 , H01L21/66
摘要： PURPOSE:To provide a connecting device having a connecting terminal capable of contacting multi-points with high density for objects to be inspected, and its production method. CONSTITUTION:A hole as a form for a contact terminal 103 is made by the aerotropic etching of a silicon wafer and, by using this form, a contact terminal 103, an insulating film 104 made of polyimide film and a lead wire 105 are formed. Moreover, a buffer layer 108 and a silicon wafer as a substrate 109 are sandwiched in one body between the insulating film 104 and a wiring substrate 107, and then the form is removed. Therefore, a lead wire 105 is connected with solder to an electrode 110a of the wiring substrate 107.

53. 发明专利

JPH0653349A WIRING STRUCTURE OF MULTICHIP MODULE SUBSTRATE 失效
公开(公告)号：JPH0653349A
公开(公告)日：1994-02-25
申请号：JP20213392
申请日：1992-07-29
申请人： HITACHI LTD
发明人： ISHINO MASAKAZU
IPC分类号： H01L23/12
摘要： PURPOSE:To minimize the floating capacity in a wiring course so as to improve the propagation property of a high-speed signal by reducing the number of through holes for connecting the surface layer of a module substrate consisting of multiple wiring layers with the lower layers gradually at a certain rate for each wiring layer, and connecting the signal between LSIs in the shortest distance. CONSTITUTION:A module substrate is composed of the five stories of four-story wiring layers a, b, c, and d, which have through hole density different in thickness direction, and one connection pad arrangement e of input and output terminals, and the numbers of through holes 12 made are reduced gradually at a certain rate from the surface layer of each story to the side of input and output terminals. And, the layer a is a face-centered lattice of 0.14mum, and the layer b tetragonal lattice of 0.14mum, the layer c a tetragonal lattice of 0.28mum, and the layers d, e are 1/4 and 1/16 times as high as the layer c in lattice density, so at the boundary between each layer, the number of through holes can be reduced. Accordingly, the number of through holes required for the connection between the upper and lower layers can be reduced by performing the mutual wiring in plane direction for each layer thereby reducing the number of junctions.

54. 发明专利

JPH0620909A EXPOSURE METHOD AND THIN-FILM MULTILAYER SUBSTRATE 失效
公开(公告)号：JPH0620909A
公开(公告)日：1994-01-28
申请号：JP17305992
申请日：1992-06-30
申请人： HITACHI LTD
发明人： YOSHIMOTO MITSUO , SHIGI HIDETAKA , YAMADA OSAMU , ISHINO MASAKAZU , INOUE TAKASHI , ABE SHINJI
IPC分类号： G03B27/32 , G03F7/20 , H01L21/027 , H01L21/30 , H05K3/00 , H05K3/46
摘要： PURPOSE:To align a surface pattern and an aligning layer by a method wherein positional dimensions from a reference position are measured previously, the quantity of displacement with the positional dimensions from the reference position of a mask patter is computed, the range of exposure is divided, and a section to be exposed is moved from the reference position so as to be aligned with a foundation pattern within the range and exposed. CONSTITUTION:Reference marks 21 on a ceramic board are detected by using a coordinate-position measuring machine. The positions of the coordinates of patters at each apex of a quadrilateral 22 are measured while using the marks 21 as reference points, and the quantity and direction of displacement from designed coordinates are computed at every exposure division unit by an arithmetic processing storage device. The optimum coordinates of exposure are computed and stored from information such as the dimensions and pattern pitches etc., of the surface pattern of the previously stored ceramic board. The optimum coordinates of exposure are aligned with the surface pattern of the ceramic board, and determined so that each layer is displaced from the surface pattern every slight section so as not to form distortion in the pattern.

55. 发明专利

JPH05198948A THICK-FILM/THIN-FILM HYBRID MULTILAYER CIRCUIT BOARD 失效
公开(公告)号：JPH05198948A
公开(公告)日：1993-08-06
申请号：JP820392
申请日：1992-01-21
申请人： HITACHI LTD
发明人： ISHINO MASAKAZU
IPC分类号： H05K3/46
摘要： PURPOSE:To maintain the adhesive strength at the interface and prevent the exfoliation between layers by preventing water, etc., from penetrating between the insulating layers of film wiring layers, in a thick-film/thin film hybrid multilayer circuit board. CONSTITUTION:The peripheral part of the first insulating layer 2 is removed by method such as dry etching, etc., and a metallic film 3 is made to cover time surface. The second insulating layer 4 is removed as far as the line a little inner from the end of the first insulating layer 2, and thereon the second wiring layer 5 is formed. Hereby, it gets into such structure that the interface between the first insulating layer and the second insulating layer is sealed with a metallic film 3. By using this structure, the penetration of moisture from the end face of the insulating layer can be prevented, and besides, this end face is bonded by the metallic film 3 large in adhesive strength, so it has great effect on the prevention of the exfoliation between layers.

56. 发明专利

JPH0461201A THIN-FILM RESISTOR 失效
公开(公告)号：JPH0461201A
公开(公告)日：1992-02-27
申请号：JP17004390
申请日：1990-06-29
申请人： HITACHI LTD
发明人： NARIZUKA YASUNORI , IKEDA SEIJI , YABUSHITA AKIRA , ISHINO MASAKAZU , KISHIDA JUICHI
IPC分类号： B41J2/335 , H01C7/00 , H05B3/12 , H05B3/14
摘要： PURPOSE:To realize a thin film resistor which is stable with time and is greatly resistant to high-power by using metallic chromium, metallic silicon, chromium silicate, silicon oxide and chromium oxide as essential components. CONSTITUTION:An increase in the resistance is suppressed by forming a chromium silicide at a high temperature for a Cr-Si-based thin-film resistor. A sputtering target to be used as a raw material for the thin film is formed of a chromium silicide and silicon. Chromium and silicon which do not form a silicide suppress a high speed which forms the silicide by heating after the film has been formed. A chromium oxide and a silicon oxide are contained in the thin film. For example, a powder which has mixed chromium disilicide (CrSi2) with silicon (Si) in a desired mixture ratio is used as a raw material, and a uniform target containing CrSi2 and Si is manufactured by using a sintering method. The resistance thin film is formed on a glass-coated ceramic substrate by a DC conventional sputtering method.

57. 发明专利

JPH03236237A METHOD AND APPARATUS FOR FORMING WIRING 失效
公开(公告)号：JPH03236237A
公开(公告)日：1991-10-22
申请号：JP3160190
申请日：1990-02-14
申请人： HITACHI LTD
发明人： NISHITANI EISUKE , TSUJIKU SUSUMU , HANIYU YOSHIAKI , ISHINO MASAKAZU
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/285
摘要： PURPOSE:To make the throughput in forming a wiring excellent without steps for applying, exposing and developing an organic light sensitive material and the like and to make it possible to cope with the small amount of production of many kinds of ICs by sequentially performing two steps for forming an active layer corresponding to the desired wiring pattern on the surface of the insulating film on a substrate and for selective CVD for metal. CONSTITUTION:A wafer 109 is conveyed into an electron-beam projecting chamber 116 by a wafer conveying mechanism. Thus the wafer is set. An electron beam is deflected, and a pattern is drawn. After the wafer 109 is conveyed into a film forming chamber 102 and set, Ar gas is introduced on the rear surface side of the wafer 109 through a gas introducing pipe 111. H2 is introduced into the film forming chamber 102. The wafer 109 receives infrared rays from wafer heating halogen lamps 106 through a quartz window 114. The wafer 109 is heated to a specified temperature. After the wafer 109 is heated to the specified temperature, WF6 gas is introduced in addition to the H2 gas. Thus W is selectively grown. The wafer 109 is cooled. The wafer 109 is taken out of the chamber, and the wiring forming step of the W is finished.

58. 发明专利

JPH031960A THERMAL HEAD 失效
公开(公告)号：JPH031960A
公开(公告)日：1991-01-08
申请号：JP13600889
申请日：1989-05-31
申请人： HITACHI LTD
发明人： YABUSHITA AKIRA , NARIZUKA YASUNORI , IKEDA SEIJI , ISHINO MASAKAZU , KAMEI TSUNEAKI
IPC分类号： B41J2/335
摘要： PURPOSE:To enhance the reliability of the wiring connection of a thermal head and, at the same time, to reduce manufacturing cost by directly utilizing the wiring conduc tor layer connected to a heating resistor as a solder connecting metal layer in the thermal head. CONSTITUTION:A photothermal resistance layer 3 and a wirig conductor layer 4 are formed on a high resistance substance 2 made of alumina ceramics in predetermined pattern shapes and an oxidation preventing protective film 51 composed, for example, of SiO2 used in both of the prevention of the oxidation of a heating resistor element and the protection of a wiring region is formed to the upper surfaces of both layers 3, 4. An abrasion-resistant layer 52 is formed to the region of the heating resistor element 1 within a specific range and a driver IC element 7 is mounted to the through- hole 8 opened to the oxidation preventing protective film 51 at a predetermined posi tion by a solder melting connection method. Herein, the wiring conductor layer 4 is constituted of an Ni-Cu alloy and the compositional ratio of said alloy is constituted so that Cu is rich in the intermediate region of the wiring conductor layer 4 and Ni is rich in the lower layer region on the wiring conductor layer 4. By this method, solder connectability and a lowering of resistance can be satisfied simultaneously and a wiring conductor can be apparently constituted of a single alloy layer.

59. 发明专利

JPH02132825A METHOD OF FILLING IN FINE HOLE WITH METAL AND CVD DEVICE FOR EXECUTING SAME 失效
公开(公告)号：JPH02132825A
公开(公告)日：1990-05-22
申请号：JP17791489
申请日：1989-07-12
申请人： HITACHI LTD
发明人： NISHITANI EISUKE , TSUJIKU SUSUMU , ISHINO MASAKAZU , KOBAYASHI HIDE , KASAHARA OSAMU , TAMARU TAKESHI , NEZU HIROKI
IPC分类号： C23C16/02 , C23C16/04 , C23C16/06 , C23C16/54 , H01L21/28 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/768 , H01L23/522
摘要： PURPOSE:To perform filling in holes which is excellent in selectivity and low in interfacial resistance by a method wherein, after performing an Ar sputter- etching and cleaning process as well as the stabilizing process of the surface of an activated insulating film, the selective chemical vapor deposition process is performed. CONSTITUTION:A substrate 9 having fine holes in an insulating film is heated in a load lock chamber 1 to be dehydrated and then carried to a sputter-etching chamber 3. Next, Ar gas is led into the chamber 3 to impress a cathode electrode 8 with high-frequency power for sputter-etching process by Ar plasma and then Cl2 gas is led in to produce Cl2 plasma for stabilizing the surface of the activated insulating film. Later, the substrate 9 is carried to a filming chamber 2; Ar is led in the rear side of the substrate 9; and H2 gas is led in to be heated. Then, WF6 in addition to the H2 gas is led in to selectively deposit W in the specified film thickness. Through these procedures, the burying process in excellent selectivity and low interfacial resistance can be performed by performing the selective chemical vapor deposition process after performing the underneath layer cleaning process and stabilizing process.

60. 发明专利

JPS61259538A SEMICONDUCTOR WAFER FEEDING BOX 失效
公开(公告)号：JPS61259538A
公开(公告)日：1986-11-17
申请号：JP10055885
申请日：1985-05-14
申请人： HITACHI LTD
发明人： ISHINO MASAKAZU , FUNATSU RYUICHI , TAKAHASHI TSUTOMU , ITO FUMIKAZU , ARAYA TATSUYA
IPC分类号： B65D85/86 , H01L21/00 , H01L21/67 , H01L21/673 , H01L21/68
摘要： PURPOSE:To stop the contamination of a semiconductor wafer to the minimum limit by feeding the wafer in a vacuum state. CONSTITUTION:A cover 1 for placing a cartridge 3 in which a plurality of semiconductor wafers 2 are charged at the upper center, and a sealed vessel 6 placed at the hole bottom on the peripheral end of the cover 1 and having a dust removing filter 5 and a leakage valve 4 are provided. When the valve 4 is connected with a vacuum supply source, the vessel 6 is maintained in a vacuum state, the lower portion of the vessel 6 and the cover 1 are held in a sealed state by the pressure difference between the exterior and the interior, and the vessel 6 is conveyed to the prescribed position in this state. Thereafter, when the valve 4 is switched and connected with the atmosphere, dusts are separated by the filter 7 from the atmospheric air, an the pressure in the chamber is raised to the same pressure as the outer cylinder. Accordingly, the cover 1 becomes openable state. Thus, the wafer 3 can be fed without contacting with the atmospheric air, thereby reducing the possibility of contaminating the wafers 3.

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