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41. 发明专利

JP3567820B2 The clock generation circuit 有权
公开(公告)号：JP3567820B2
公开(公告)日：2004-09-22
申请号：JP29936199
申请日：1999-10-21
申请人：三菱電機株式会社
发明人：隆則東海林
IPC分类号： H03K23/64

42. 发明专利

JP3561657B2 Variable frequency equipment 有权
公开(公告)号：JP3561657B2
公开(公告)日：2004-09-02
申请号：JP14514299
申请日：1999-05-25
申请人：三洋電機株式会社 , 鳥取三洋電機株式会社
发明人：育亮鷲見
IPC分类号： H03K23/64 , H03L7/183

43. 发明专利

JP3522584B2 Phase comparator and the power-saving operation control method, and a semiconductor integrated circuit 有权
公开(公告)号：JP3522584B2
公开(公告)日：2004-04-26
申请号：JP12062099
申请日：1999-04-27
申请人：富士通株式会社
发明人：浩志馬場
IPC分类号： H03K23/64 , H03D13/00 , H03L7/085 , H03L7/18 , H03L7/193 , H03L7/199
CPC分类号： H03L7/193 , H03D13/00 , H03D2200/0084 , H03K23/64 , H03L7/199

44. 发明专利

JP3519346B2 Circuit device for the frequency divider 有权
公开(公告)号：JP3519346B2
公开(公告)日：2004-04-12
申请号：JP2000196983
申请日：2000-06-29
申请人：インフィネオンテクノロジースアクチエンゲゼルシャフト
发明人：ハイネンシュテファン
IPC分类号： H03K23/64 , H03K23/66 , H03L7/193
CPC分类号： H03K23/667 , H03L7/193

45. 发明专利

JP2004056634A Signal processing apparatus, non-integral frequency divider and fractional n-phase lock loop synthesizer using the same 有权
$Signal processing apparatus, non-integral frequency divider and fractional n-phase lock loop synthesizer using the same$
公开(公告)号：JP2004056634A
公开(公告)日：2004-02-19
申请号：JP2002213888
申请日：2002-07-23
申请人： Nec Corp , 日本電気株式会社
发明人： MATSUNO NORIO
IPC分类号： H03K23/64 , H03L7/08 , H03L7/183 , H03L7/197 , H03M3/02 , H04B14/06
CPC分类号： H03L7/1976
摘要： PROBLEM TO BE SOLVED: To provide a signal processing apparatus with a small circuit scale, a non-integral frequency divider and a fractional N PLL (phase lock loop) synthesizer having the same. SOLUTION: An adder 8 and a delay device 10 constitute a 9-bit accumulator, output of an adder 2 is inputted and output of 3-input NAND gate 30 is connected with the remaining least significant bit input. An adder 13 and a delay device 15 constitute a 6-bit accumulator and output of the adder 8 is inputted. An adder 18 and a delay device 20 constitute a 4-bit accumulator and output of the adder 13 is inputted. Output of the delay device 20 is inputted in the 3-input NAND gate 30. Overflow signals 22 to 25 of each accumulator are inputted in a signal processing section 27, the sum of the overflow signal 22, first-order differentiation of the overflow signal 23, second-order differentiation of the overflow signal 24 and third-oder differentiation of the overflow signal 25 is obtained and the result is outputted from an output terminal 28. COPYRIGHT: (C)2004,JPO

46. 发明专利

JP3439351B2 失效
公开(公告)号：JP3439351B2
公开(公告)日：2003-08-25
申请号：JP28474198
申请日：1998-09-22
IPC分类号： H03K23/64 , H03L7/183 , H03L7/197

47. 发明专利

JP2003069421A Counter timing control circuit and counter timing control method 审中-公开
标题翻译：计数器时序控制电路和计数器时序控制方法
公开(公告)号：JP2003069421A
公开(公告)日：2003-03-07
申请号：JP2001257868
申请日：2001-08-28
申请人： Nec Miyagi Ltd , 宮城日本電気株式会社
发明人： KIKUCHI YUICHI
IPC分类号： H03K23/64
摘要： PROBLEM TO BE SOLVED: To provide a counter timing control circuit that can control a synchronization operation of counters in a control system and a system to be controlled at a low speed.
SOLUTION: A timing generator 14 outputs timing signals (111, 112), (121, 122) and (131, 132) to control the counters 11, 12 and 13 of the control system. A duty encoder 15 generates a frame according to an externally received operating clock 100, uses a head of the frame as an operation reference and transmits a control signal 200 resulting in coding the operation reference by each frame period and generating it. A duty encoder 25 decodes an output of the duty encoder 15 to give the timing signals (111, 112), (121, 122) and (131, 132) to the counters 21, 22 and 23 of the system to be controlled respectively to control them.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种可以控制控制系统中的计数器的同步操作和要以低速控制的系统的计时定时控制电路。解决方案：定时发生器14输出定时信号（111,112），（121,122）和（131,132）以控制控制系统的计数器11,12和13。占空比编码器15根据外部接收的操作时钟100生成帧，使用帧的头作为操作基准，并且发送控制信号200，导致对每个帧周期的操作参考进行编码并生成它。占空比编码器25对占空比编码器15的输出进行解码，以将待控制的系统的计数器21,22和23的定时信号（111,112），（121,122）和（131,132）分别给予控制他们

48. 发明专利

JP2002271190A CLOCK SUPPLY BIAS CIRCUIT AND SINGLE-PHASE CLOCK DRIVE DIVIDING CIRCUIT 失效
公开(公告)号：JP2002271190A
公开(公告)日：2002-09-20
申请号：JP2001072538
申请日：2001-03-14
申请人： NEC CORP
发明人： GLENN KEIJI MURATA
IPC分类号： G06F1/08 , H03K5/151 , H03K21/02 , H03K23/64
摘要： PROBLEM TO BE SOLVED: To solve the problem in which a clock voltage is usually set half as large a s the operating voltage, so as to increase gm of an N-type or a P-type MOS transistor to a maximum, when the DFF circuit of a dividing circuit is driven by the use of single-phase clock signals, but the gm of the N-type MOS transistor cannot be made sufficiently large through this method, and method is not capable of coping with the requirements for input signals of higher frequencies in future. SOLUTION: A single-phase clock CLK 0 is divided into clock signals CLK1 for driving an NMOS transistor and clock signals CLK2 for driving a PMOS transistor. When the divided clock signals are inputted into DFFs 1, 2, and 3 constituting in a dividing circuit, the gm of the N-type or P-type MOS transistor can be set higher than in the conventional cases, so that a single-phase clock drive dividing circuit can be improved much further in frequency characteristics than the conventional.

49. 发明专利

JP2002519923A 失效
公开(公告)号：JP2002519923A
公开(公告)日：2002-07-02
申请号：JP2000557549
申请日：1999-06-11
IPC分类号： H03K23/64 , H03K23/66

50. 发明专利

JP2002185310A PRE-SCALER DEVICE AND DIVIDING METHOD 失效
公开(公告)号：JP2002185310A
公开(公告)日：2002-06-28
申请号：JP2000384082
申请日：2000-12-18
申请人： YASKAWA ELECTRIC CORP
发明人： SAKATA SHUNICHI , KAJIWARA SHINSUKE
IPC分类号： G06F1/08 , H03K5/00 , H03K23/64
摘要： PROBLEM TO BE SOLVED: To provide a pre-scaler circuit capable of obtaining a clock signal of a desirable frequency by small circuits with respect to an input of the clock signal of a different frequency. SOLUTION: In a pre-scaler device, a plurality of clock signals of a different frequency are input as a first basic clock signal, and the basic clock signal is divided to generate the clock signal of a desirable frequency. The pre-sealer device has a plurality of first pre-scalers 2, 3 and a single second pre-scaler 4. In the plurality of first pre-scalers 2, 3, when a common divisor of a frequency of a plurality of the first basic clock signals is an intermediate frequency, each of the plurality of basic clock signals of the different frequency is input, and each of the second basic clock signals of the intermediate frequency is generated. In the single second pre-scaler 4, the second basic clock signal output from the plurality of first pre-scalers is input and divided to generate the clock signal of the desirable frequency.

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