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41. 发明专利

JP3868505B2 Method and circuit for generating a high-speed counting 失效
公开(公告)号：JP3868505B2
公开(公告)日：2007-01-17
申请号：JP53878498
申请日：1998-03-05
申请人：マイクロン・テクノロジー・インコーポレーテッドMicron Technology,Inc.
发明人：エイ．マニング，トロイ
IPC分类号： H03K21/00 , H03K23/00 , H03K23/44 , H03K23/54
CPC分类号： H03K23/44 , H03K23/54

42. 发明专利

JPS5944812B2 JPS5944812B2 - 失效
公开(公告)号：JPS5944812B2
公开(公告)日：1984-11-01
申请号：JP1208478
申请日：1978-02-06
申请人： Tokyo Shibaura Electric Co
发明人： KATAKURA MASAYUKI
IPC分类号： H03K3/64 , H03K23/52 , H03K23/54
CPC分类号： H03K23/54

43. 发明专利

JPS59181831A Variable frequency divider 失效
标题翻译：可变频分频器
公开(公告)号：JPS59181831A
公开(公告)日：1984-10-16
申请号：JP5596483
申请日：1983-03-31
申请人： Toshiba Corp
发明人： OOIDA YOSHIO
IPC分类号： H03K23/64 , H03K23/54 , H03K23/66 , H04B1/26
CPC分类号： H03K23/667 , H03K23/54
摘要： PURPOSE: To reduce the power consumption by using a shift register for feedback, a shift register for delay and a shift register for control so as to increase the maximum operating speed near the operating speed of the operating shift register itself.
CONSTITUTION: When a switching signal -PE is at a high level, an NOR gate 26 is at a low level, an AND gate AND is inhibited so as to perform 1/4-frequency-division by the shift register 21 for feedback and the shift register 22 for delay and a 1/8-frequency-division output is obtained from an expander circuit 24. When the switching signal -PE is at a low level, the pulse is counted by one more than before by means of the shift register 21 for feedback and the shift register 22 for delay attended with the operation of the shift register 23 for control with an AND gate AND, a 1/9-frequency-division output is obtained from the expander circuit 24 and the maximum operating speed is increased near the operating speed of the operating shift register itself.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过使用移位寄存器进行反馈以减少功耗，延迟移位寄存器和用于控制的移位寄存器，以便在操作移位寄存器本身的运行速度附近增加最大工作速度。构成：当开关信号-PE处于高电平时，或非门26处于低电平，禁止AND门AND，以便通过移位寄存器21执行1/4分频以进行反馈，并且移位寄存器22用于延迟，并且从扩展器电路24获得1 / 8-分频输出。当开关信号-PE处于低电平时，脉冲通过移位寄存器 21用于反馈，移位寄存器22用于与AND门AND进行控制的移位寄存器23的操作相关，从扩展器电路24获得1/9分频输出，并且最大工作速度增加接近操作移位寄存器本身的操作速度。

44. 发明专利

JPS5783932A Frequency dividing circuit 失效
标题翻译：频率分流电路
公开(公告)号：JPS5783932A
公开(公告)日：1982-05-26
申请号：JP15928780
申请日：1980-11-11
申请人： Matsushita Electric Ind Co Ltd
发明人： TAKAGI YOSHIYUKI
IPC分类号： G10H5/00 , H03K23/54 , H03K23/64
CPC分类号： H03K23/54
摘要： PURPOSE:To obtain a highest-octave-scale generator of simple circuit constitution for an electronic musical instrument by inputting the frequency division output of a longest-period feedback shift register to a 1/2 frequency divider and by using its output as a sound-source signal. CONSTITUTION:A main oscillation signal from an input 11 is passed through an inverter 12 to obtain an in-phase and an out-of-phase signal, driving a shift register 13. The output of an AND circuit 15 and an external reset 17 are inputted to an OR circuit 18, whose output sets the register 13 in response to a following clock. Consequently, the shift register is initialized when going to a prescribed final value set by the AND circuit 15, thereby dividing the frequency of the main oscillation signal 11 by an optional integer. The frequency division output which is the output of the AND circuit 15 is inputted to a 1/2 frequency divider 19 for frequency division, obtaining frequency division output 20-29 of respective stages. The 1/2 frequency divider 19 is reset with the external reset signal 17.
摘要翻译：目的：为了通过将最长周期反馈移位寄存器的分频输出输入到1/2分频器并通过使用其输出作为声音分频器来获得用于电子乐器的简单电路结构的最高八度范围的发生器，源信号。构成：来自输入端11的主振荡信号通过反相器12以获得驱动移位寄存器13的同相和异相信号。与电路15和外部复位17的输出为输入到或电路18，其输出响应于后续时钟设置寄存器13。因此，当由AND电路15设定的规定的最终值时，移位寄存器被初始化，从而将主振荡信号11的频率除以可选的整数。作为AND电路15的输出的分频输出被输入到1/2分频器19进行分频，得到各级的分频输出20-29。 1/2分频器19由外部复位信号17复位。

45. 发明专利

JPS5761338A Counter circuit 失效
标题翻译：计数器电路
公开(公告)号：JPS5761338A
公开(公告)日：1982-04-13
申请号：JP13622480
申请日：1980-09-30
申请人： Fujitsu Ltd
发明人： HIROME MASASHI
IPC分类号： H03K21/02 , H03K23/66
CPC分类号： H03K21/02 , H03K23/54
摘要： PURPOSE:To make a frequency division circuit unnecessary, by obtaining the alternating pulse having period of two times of set value of a counter circuit by utilizing the flip-flop of the retaining on the higher rank of a counter circuit. CONSTITUTION:In case of periodical hexamerous system counter, flip-flop of the 4th stage of the higher rank of the 4 bits binary counter 1 is retained. Logical output of ''AND NOT'' circuit 2 becomes 0 when the counter value of this circuit is 5, and by the next clock, this hexamerous counter is set in initial condition. Output condition of an output terminal Q3 is read from an input terminal P3 with the inversed condition by the ''NOT'' circuit 3 by performing this clock. Output of the terminal Q3 is inversed. Hereinafter these operations are repeatedly executed. Then, alternating pulse having the period of 12 clocks is obtained at the output terminal Q3, i.e. alternating pulse having the period of two times of the set value in the counter circuit can be obtained.
摘要翻译：目的：为了使分频电路不必要，通过利用计数器电路的较高级别的保持触发器获得具有计数器电路的设定值的两倍周期的交替脉冲。构成：在周期性六元系统计数器的情况下，保留4位二进制计数器1的较高等级的第4级的触发器。当该电路的计数器值为5时，“AND NOT”电路2的逻辑输出为0，并且在下一个时钟下，该六进制计数器设置为初始状态。通过执行该时钟，从具有“NOT”电路3的反转状态从输入端子P3读出输出端子Q3的输出状态。端子Q3的输出反相。以下重复执行这些操作。然后，在输出端子Q3处获得具有12个时钟周期的交替脉冲，即可以获得具有计数器电路中设定值的两倍周期的交替脉冲。

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