会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2011055462A
    • 2011-03-17
    • JP2010086934
    • 2010-04-05
    • Hynix Semiconductor Inc株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
    • PARK JEONG-HOON
    • H03K5/00G06F1/08H03K5/26H03K19/0175H03K19/0948
    • H03K23/44G06F1/08G06F1/12G11C7/222
    • PROBLEM TO BE SOLVED: To provide a clock alignment training operation required for a high-speed semiconductor device. SOLUTION: This semiconductor device includes: a clock input portion (200) to input a system clock and a data clock thereto; a clock frequency dividing section (220) to generate a plurality of multi-phase data frequency division clocks each of which has a predetermined phase difference by dividing a frequency of the data clock and to determine whether or not phases of the multi-phase data frequency division clocks can be reversed in response to a frequency division control signal; a first phase detecting section (240) to detect a phase of the system clock based on a phase of a predetermined first selected clock among the multi-phase data frequency division clocks and to determine a level of the frequency division control signal in response to the detected result; a second phase detecting section (260) to detect a phase of the system clock based on a phase of a predetermined second selected clock among the multi-phase data frequency division clocks and to generate a training information signal in response to the detected result; and a signal transmission section (270) for transmitting the training information signal to the outside. COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:提供高速半导体器件所需的时钟对准训练操作。 解决方案:该半导体器件包括:时钟输入部分(200),用于向其输入系统时钟和数据时钟; 时钟分频部(220),用于生成多个数据分频时钟,通过对数据时钟的频率进行分频而具有预定的相位差,并且确定多相数据频率的相位 分频时钟可以响应于分频控制信号反转; 第一相位检测部分(240),用于基于多相数据分频时钟中的预定的第一选定时钟的相位来检测系统时钟的相位,并且响应于所述多相数据分频时钟来确定分频控制信号的电平 检测结果; 第二相位检测部分,用于基于所述多相数据分频时钟中的预定的第二选定时钟的相位来检测所述系统时钟的相位,并响应于所述检测结果产生训练信息信号; 以及用于将训练信息信号发送到外部的信号传输部分(270)。 版权所有(C)2011,JPO&INPIT
    • 6. 发明专利
    • Frequency divider and its control method
    • 频率分配器及其控制方法
    • JP2008005446A
    • 2008-01-10
    • JP2006175931
    • 2006-06-26
    • Matsushita Electric Ind Co Ltd松下電器産業株式会社
    • SHIMADA MIKIHIRO
    • H03K23/64H03K19/096
    • H03K23/66H03K23/42H03K23/44
    • PROBLEM TO BE SOLVED: To solve the problem of increase in size and cost of a frequency divider for outputting a plurality of output signals which differ in division ratios requires a plurality of frequency divider circuits more than the number of division ratios to be output.
      SOLUTION: The frequency divider is provided with a plurality of latch circuits 11, 13 to which a clock signal 17 and an inverse clock signal 18 are inputted respectively and connected in series, an inverter circuit 16 into which an output signal of the latch circuit 11 connected at the end out of the latch circuits 11, 13 is inputted, an output terminal 19 to which an output of the inverter circuit 16 is connected, and a plurality of feedback paths 14, 15 which connect the output of the inverter circuit 16 to an input of the latch circuits 11, 13, respectively. Furthermore, the frequency divider is provided with a switching circuit 12 which switches connections of the plurality of feedback paths 14, 15 so as to input the output signal of the inverter circuit 16 only into one of the plurality of the latch circuits 11, 13.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题为了解决用于输出分频比不同的多个输出信号的分频器的尺寸和成本增加的问题,需要多于分频比的分频电路数量 输出。 解决方案:分频器设置有分别输入时钟信号17和反时钟信号18的多个锁存电路11,13,串联连接的反相器电路16,其中输出信号 输入在锁存电路11,13的端部连接的锁存电路11,连接有逆变器电路16的输出的输出端子19和连接逆变器电路11,13的输出的多个反馈通路14,15 电路16分别连接到锁存电路11,13的输入端。 此外,分频器设置有切换电路12,其切换多个反馈路径14,15的连接,以将逆变器电路16的输出信号仅输入到多个锁存电路11,13中的一个。 版权所有(C)2008,JPO&INPIT
    • 7. 发明专利
    • Electronic circuit, divider, and radio equipment
    • 电子电路,分路器和无线电设备
    • JP2007097148A
    • 2007-04-12
    • JP2006220002
    • 2006-08-11
    • Matsushita Electric Ind Co Ltd松下電器産業株式会社
    • HOSOKAWA YOSHIFUMISAITO NORIAKISHIMIZU KATSUTO
    • H03K3/282H03K23/00H04B1/30
    • H03K3/289H03K23/44
    • PROBLEM TO BE SOLVED: To widen a dividable frequency band without performing variable control of a load circuit.
      SOLUTION: A master stage 101 comprises: a differential circuit including a transistor 1 and a transistor 2; a differential circuit including a transistor 3 and a transistor 4; a differential circuit including a transistor 5 and a transistor 6; a load circuit 7 (first load circuit); a load circuit 8 (second load circuit); and a current source transistor 9. The load circuit 7 (first load circuit) includes an inductor 7A (first inductor), an inductor 7B (fifth inductor), and a capacitor 7C (first capacitor). The inductor 7B and the capacitor 7C constitute a parallel resonant circuit (first LC parallel resonant circuit) which is connected to the inductor 7A in series.
      COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:在不执行负载电路的可变控制的情况下扩大可分频频带。 解决方案:主级101包括:包括晶体管1和晶体管2的差分电路; 包括晶体管3和晶体管4的差分电路; 包括晶体管5和晶体管6的差分电路; 负载电路7(第一负载电路); 负载电路8(第二负载电路); 电流源晶体管9.负载电路7(第一负载电路)包括电感器7A(第一电感器),电感器7B(第五电感器)和电容器7C(第一电容器)。 电感器7B和电容器7C构成串联连接到电感器7A的并联谐振电路(第一LC并联谐振电路)。 版权所有(C)2007,JPO&INPIT