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41. 发明专利

JP2008538591A Ruthenium-based material and ruthenium alloy 审中-公开
公开(公告)号：JP2008538591A
公开(公告)日：2008-10-30
申请号：JP2008507610
申请日：2005-04-21
申请人：ハネウエル・インターナシヨナル・インコーポレーテツド
发明人：トルオン，ニコール , プラター，ロバート , モラーレス，ダイアナ , リー，イール
IPC分类号： C23C14/14 , C22C5/04 , C23C14/06 , C23C14/34 , C23C16/06 , H01B1/02 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L23/52
CPC分类号： C22C5/04 , B32B15/018 , C23C14/0036 , C23C14/0641 , C23C14/165 , C23C14/3414 , C23C14/58 , H01L21/28079 , H01L21/28088 , H01L21/2855 , H01L21/76843 , H01L21/76846 , H01L21/76873 , H01L29/495 , H01L29/4966 , H01L2924/0002 , Y10T428/1266 , Y10T428/12806 , Y10T428/12819 , Y10T428/12826 , Y10T428/1284 , H01L2924/00
摘要： An alloy for use in vapor deposition or atomic layer deposition is described herein that includes ruthenium and at least one element from group IV, V or VI of the Periodic Chart of the Elements or a combination thereof. In addition, a layered material is described herein that comprises at least one layer that includes a ruthenium-based material or ruthenium-based alloy and at least one layer that includes at least one element from group IV, V or VI of the Periodic Chart of the Elements or a combination thereof.

42. 发明专利

JP2008211191A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2008211191A
公开(公告)日：2008-09-11
申请号：JP2008014407
申请日：2008-01-25
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所
发明人： JINBO YASUHIRO , ISA TOSHIYUKI , HONDA TATSUYA
IPC分类号： H01L21/02 , H01L21/20 , H01L21/336 , H01L27/12 , H01L29/786 , H01L51/50 , H05B33/10 , H05B33/14
CPC分类号： H01L27/3258 , H01L21/02565 , H01L21/2026 , H01L27/12 , H01L27/1214 , H01L27/1266 , H01L27/283 , H01L27/3274 , H01L28/40 , H01L29/24 , H01L29/42356 , H01L29/45 , H01L29/4908 , H01L29/495 , H01L29/66969 , H01L29/78603 , H01L29/7869 , H01L51/003 , H01L51/56 , H01L2227/323 , H01L2227/326 , H01L2251/5338
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a flexible semiconductor device that exfoliates a device manufactured in a process at a relatively low temperature (lower than 500°C) from a substrate. SOLUTION: A molybdenum film is formed on a glass substrate and a molybdenum oxide film is formed on its surface using an existing manufacturing device of a large glass substrate. A nonmetal inorganic film and an organic compound film are laminated on the molybdenum oxide film, and after the device that is manufactured in a process at a relatively low temperature (lower than 500°C) is formed on the organic compound film, the device is exfoliated from the glass substrate. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决问题的方案：提供一种制造柔性半导体器件的方法，该柔性半导体器件从基板剥离在相对低的温度（低于500℃）的工艺中制造的器件。解决方案：在玻璃基板上形成钼膜，使用现有的大型玻璃基板的制造装置，在其表面上形成氧化钼膜。在氧化钼膜上层叠非金属无机膜和有机化合物膜，在有机化合物膜上形成在相对低温（低于500℃）的工序中制造的器件后，器件为从玻璃基板剥离。版权所有（C）2008，JPO＆INPIT

43. 发明专利

JP2008515205A Structures and methods for fabricating a strained channel field effect transistor using a sacrificial spacer 有权
公开(公告)号：JP2008515205A
公开(公告)日：2008-05-08
申请号：JP2007533774
申请日：2005-09-29
申请人：インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation , 株式会社東芝
发明人：オー、サンヒュン , チェン、ホワチー , チダンバラオ、デュレセティ , パンダ、シッダールタ , ユートモ、ヘンリー、ケー , ラウシュ、ウェルナー、エー , 力佐藤
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor ("FET") is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

44. 发明专利

JP2008507856A Planarization of semiconductor structure for replacement metal gate formation 有权
公开(公告)号：JP2008507856A
公开(公告)日：2008-03-13
申请号：JP2007523624
申请日：2005-07-14
申请人：インテルコーポレイション
发明人：カヴァリエロス，ジャック , シャー，ウダイ , ショー，ロバート , ダッタ，サマン , ドクジー，マーク , バーンズ，クリス , ブラスク，ジャスティン , メッツ，マシュー
IPC分类号： H01L29/78 , H01L21/283 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28088 , H01L21/31111 , H01L21/32134 , H01L21/823807 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要：窒化物および充填層を含む犠牲ゲート構造は、金属ゲート電極と置換される。金属ゲート電極は、充填層で被覆された窒化物層で再度被覆される。窒化物および充填層の置換によって、歪みが再導入され、エッチング停止層が提供される。

45. 发明专利

JP2007529115A Power semiconductor device and a method for manufacturing the same 有权
公开(公告)号：JP2007529115A
公开(公告)日：2007-10-18
申请号：JP2006547577
申请日：2004-12-28
申请人：フェアチャイルド・セミコンダクター・コーポレーション
发明人：ペーターエイチ．ウィルソン , アランエルバンハウイー , クリストファービー．ココン , スティーブンピー．サップ , ババックエス．サニ , アショクシャラ
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L21/76 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/165 , H01L29/267 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/861
CPC分类号： H01L29/7802 , H01L21/26506 , H01L21/26586 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/165 , H01L29/267 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/4933 , H01L29/495 , H01L29/66734 , H01L29/7804 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2224/16245 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

46. 发明专利

JP2007067225A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007067225A
公开(公告)日：2007-03-15
申请号：JP2005252359
申请日：2005-08-31
申请人： Toshiba Corp , 株式会社東芝
发明人： IINUMA TOSHIHIKO , AKUTSU HARUKO , SUGURO KYOICHI
IPC分类号： H01L21/28 , H01L21/336 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/495 , H01L29/4966 , H01L29/665 , H01L29/66795 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve the flatness of an interface between a source/drain regions and a nickel silicide film. SOLUTION: A nickel film containing an erbium is formed on the source/drain regions 5sd. Subsequently, the source/drain regions 5sd and the nickel film containing the erbium are heated to form a nickel silicide film 9. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提高源极/漏极区域与硅化镍膜之间的界面的平坦度。解决方案：在源极/漏极区域5sd上形成含有铒的镍膜。随后，将源极/漏极区域5sd和含有铒的镍膜加热以形成硅化镍膜9.版权所有（C）2007，JPO＆INPIT

47. 发明专利

JP2007019513A Semiconductor device having buried gate, and manufacturing method thereof 审中-公开
标题翻译：具有盖栅的半导体器件及其制造方法
公开(公告)号：JP2007019513A
公开(公告)日：2007-01-25
申请号：JP2006186868
申请日：2006-07-06
申请人： Infineon Technologies Ag , インフィネオンテクノロジーズアクチエンゲゼルシャフト
发明人： HIELEMANN MATTHIAS , LINDSAY RICHARD
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/42356 , H01L21/26586 , H01L21/28097 , H01L21/28194 , H01L21/823807 , H01L21/823828 , H01L21/823885 , H01L27/088 , H01L27/10876 , H01L29/1083 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66575 , H01L29/6659 , H01L29/66613 , H01L29/66621
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of establishing compatibility between reduction in a short channel effect of a buried gate transistor and an increase in superimposition between the transistor and the gate, and a manufacturing method thereof.
SOLUTION: This semiconductor device 202 is provided with concave portions 118 formed in a first region 104, a second region 106 and separation regions 108 respectively; and a dielectric layer 120 for backing the concave portions 118 so as to have a uniform thickness, on a substrate 102. This manufacturing method includes a process of forming the separation regions 108 between the first region 104 and the second region 106 in the substrate 102; a process of forming the concave portions 118 on the substrate surface; and a process of uniformly covering the concave portions 118 with an oxide 120. The method further includes a process of doping a channel region 124 disposed under the bottom surface of each of the concave portions 118, a process of depositing an electrode material 126 on each of the concave portions 118, and a process of forming source/drain regions.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件及其制造方法，该半导体器件能够在降低掩埋栅晶体管的短沟道效应和晶体管与栅极之间的叠加的增加方面建立兼容性。解决方案：该半导体器件202设置有分别形成在第一区域104，第二区域106和分离区域108中的凹部118。以及在衬底102上用于背衬凹部118以均匀厚度的电介质层120.该制造方法包括在衬底102中的第一区域104和第二区域106之间形成分离区域108的工艺 ; 在基板表面上形成凹部118的工序; 以及用氧化物120均匀地覆盖凹部118的工艺。该方法还包括掺杂设置在每个凹部118的底表面下方的沟道区124的工艺，每个凹部118的电极材料126沉积的凹部118，以及形成源极/漏极区域的工艺。版权所有（C）2007，JPO＆INPIT

48. 发明专利

JP2007019177A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007019177A
公开(公告)日：2007-01-25
申请号：JP2005197835
申请日：2005-07-06
申请人： Toshiba Corp , 株式会社東芝
发明人： ONO TAMASHIRO
IPC分类号： H01L29/78 , H01L29/786
CPC分类号： H01L29/47 , H01L21/32115 , H01L29/42368 , H01L29/495 , H01L29/513 , H01L29/515 , H01L29/517 , H01L29/66545 , H01L29/66643 , H01L29/7839
摘要： PROBLEM TO BE SOLVED: To provide a Schottky MOSFET which controls the fluctuation of current driving force.
SOLUTION: A semiconductor device comprises one pair of source and drain regions consisting of metal or metal silicide, formed face to face on a semiconductor layer and on the semiconductor substrate; a first insulating film formed at least on the semiconductor layer between the source region and the drain region; a second insulating film formed on the first insulating film whose dielectric constant is higher than that of the first insulating film; and a gate electrode formed on the second insulating film. The length of the second insulating film measured in the opposite direction of the source region and the drain region is shorter than the length of the gate electrode measured in the opposite direction of the source region and the drain region.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种控制电流驱动力波动的肖特基MOSFET。解决方案：半导体器件包括一对由金属或金属硅化物组成的源极和漏极区域，在半导体层上和半导体衬底上面对面地形成; 至少形成在所述源极区域和所述漏极区域之间的所述半导体层上的第一绝缘膜; 形成在第一绝缘膜上的第二绝缘膜，其介电常数高于第一绝缘膜的介电常数; 以及形成在所述第二绝缘膜上的栅电极。在源极区域和漏极区域的相反方向上测量的第二绝缘膜的长度短于在源极区域和漏极区域的相反方向上测量的栅极电极的长度。版权所有（C）2007，JPO＆INPIT

49. 发明专利

JP2006524438A By introducing silicon, a method of forming a metal gate structure in which fine adjustment of the work function 审中-公开
公开(公告)号：JP2006524438A
公开(公告)日：2006-10-26
申请号：JP2006513131
申请日：2004-04-19
申请人：アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated
发明人：ウークリスティー , エヌ．パンジェーンズ , インジンソン , アール．ベセルポール , バンエヌジーオーミン
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3215 , H01L21/336 , H01L29/423 , H01L29/49
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28088 , H01L21/3215 , H01L29/495 , H01L29/4966 , H01L29/78
摘要：制御された仕事関数を備えるメタルゲート（３０）を有する半導体構造を形成する方法である。この方法は、チャネルによって分離された活性領域（１２）を備えた基板およびチャネル上および絶縁層（２０）内の一時的ゲート（１６）を有するプレカーサを形成するステップを含んでいる。この一時的ゲート（１６）を除去して、絶縁層（２０）中に底面およびサイドウォールを備える凹部（２２）を形成する。非シリコン金属を含んでいるメタル層（２６）を、この凹部（２２）にたい積する。このメタル層（２６）中にシリコンを導入し、メタル層（２６）上にメタルをたい積する。シリコンの導入は、熱的シラン処理により行われる。この熱的シラン処理は、メタル層（２６）をたい積する前、後、またはその前後に実行される。メタル層（２６）中に導入するシリコンの量によって、形成されるメタルゲート（３０）の仕事関数を制御する。

50. 发明专利

JP2006269520A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006269520A
公开(公告)日：2006-10-05
申请号：JP2005081981
申请日：2005-03-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YOSHIGAMI JIRO , INOUE MASAO , MORI KENICHI , SAKASHITA SHINSUKE
IPC分类号： H01L29/78 , H01L21/28 , H01L29/423 , H01L29/49
CPC分类号： H01L29/495 , H01L21/28176 , H01L29/4966 , H01L29/517 , H01L29/66575
摘要： PROBLEM TO BE SOLVED: To stabilize a gate electrode and to keep a desired work function, even after a heat treatment is conducted in a semiconductor device.
SOLUTION: The semiconductor device comprises: a semiconductor substrate 6; a gate insulation film 1 formed on the semiconductor substrate 6 in contact with it; and the gate electrode 2 formed of a metal nitride or metal nitriding silicide above the gate insulation film 1. Between the gate insulation film 1 and the gate electrode 2, a buffer layer 3 is interposed to prevent the diffusion of nitrogen and silicon. Preferably, the buffer layer 3 has a thickness of 5 nm or less. It is also preferable that the buffer layer 3 contains a titanium film, if the gate electrode 2 contains a Ti element and the gate insulation film 1 contains a Hf element.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使在半导体器件中进行热处理之后，为了稳定栅电极并保持所需的功函数。解决方案：半导体器件包括：半导体衬底6; 形成在与其接触的半导体基板6上的栅极绝缘膜1; 以及由栅极绝缘膜1上方的金属氮化物或金属氮化硅化物形成的栅极电极2.在栅极绝缘膜1和栅极电极2之间插入有缓冲层3，以防止氮和硅的扩散。优选地，缓冲层3的厚度为5nm以下。如果栅电极2含有Ti元素并且栅极绝缘膜1含有Hf元素，则缓冲层3也优选含有钛膜。版权所有（C）2007，JPO＆INPIT

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