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1. 发明专利

JP2008210969A Semiconductor device and its manufacturing method, and semiconductor memory device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法及半导体存储器件及其制造方法
公开(公告)号：JP2008210969A
公开(公告)日：2008-09-11
申请号：JP2007045736
申请日：2007-02-26
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： INOUE MASAO , MIZUTANI SEIJI , YOSHIGAMI JIRO , TSUCHIMOTO JUNICHI , NOMURA KOJI
IPC分类号： H01L29/78 , H01L21/314 , H01L21/316 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which includes, as a gate insulation film, an Hf oxide film which can tolerate a heat treatment at 1,000°C or above which is indispensable for manufacturing a CMOS device.
SOLUTION: The semiconductor device includes a gate structure 10 which includes a laminate consisting of a gate insulation film 11 formed at a predetermined place on the surface of a semiconductor substrate 1 and a gate electrode 12, and a source and a drain region 21 formed on both sides in the line width direction of the gate structure 10 on the surface of the semiconductor substrate 1. The gate insulation film 11 consists of an HfO
2 film having a Zr concentration of 200 ppm or below.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其包括作为栅极绝缘膜的可耐受在1000℃以上的热处理的Hf氧化物膜，其对于制造CMOS器件是不可或缺的。解决方案：半导体器件包括栅极结构10，栅极结构10包括由在半导体衬底1的表面上的预定位置处形成的栅极绝缘膜11和栅电极12以及源极和漏极区域 21形成在半导体衬底1的表面上的栅极结构10的线宽度方向的两侧。栅极绝缘膜11由Zr浓度为200ppm的HfO 2 SBO 2膜或下面。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008066378A Semiconductor device, and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008066378A
公开(公告)日：2008-03-21
申请号：JP2006240279
申请日：2006-09-05
申请人： Matsushita Electric Ind Co Ltd , Renesas Technology Corp , 松下電器産業株式会社 , 株式会社ルネサステクノロジ
发明人： YAMAMOTO KAZUHIKO , ISHINAGA ATSUSHI , SATO YOSHIHIRO , INOUE MASAO , SAKASHITA SHINSUKE , YOSHIGAMI JIRO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To actualize a semiconductor device including a full-silicide gate electrode having a stable work function value and a threshold value.
SOLUTION: The semiconductor device is provided with a gate insulating film 15a formed on a semiconductor substrate and a gate electrode 23 formed on the gate insulating film. The gate electrode 23 is a full silicide gate electrode including a metal silicide film formed by laminating a plurality of crystal grain layers.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：实现包括具有稳定的功函数值和阈值的全硅化物栅电极的半导体器件。解决方案：半导体器件设置有形成在半导体衬底上的栅极绝缘膜15a和形成在栅极绝缘膜上的栅电极23。栅电极23是包括通过层叠多个晶粒层而形成的金属硅化物膜的全硅化物栅电极。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006295131A Semiconductor apparatus and method for manufacturing same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：JP2006295131A
公开(公告)日：2006-10-26
申请号：JP2006038918
申请日：2006-02-16
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MIZUTANI SEIJI , INOUE MASAO , YOSHIGAMI JIRO , TSUCHIMOTO JUNICHI , NOMURA KOJI , SHIMAMOTO YASUHIRO
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L29/1083 , H01L29/6659
摘要： PROBLEM TO BE SOLVED: To provide a semicondutor apparatus which can reduce power dissipation and to provide a method for manucfacturing the same.
SOLUTION: The MISFET 10 is provided with a p-type substrate 1 having a channel region 20 of impurity concentration C, an SiO
2 insulation film 11 formed on the channel region 20, and an HfSiON insulation film 12 formed on the insulation film 11. Assuming another MISFET which is provided with a substrate having impurity concentration C and composed of the same material as that of the substrate 1, and an insulation film composed of SiON only formed on the channel region; the impurity concentration C of the channel region 20 is so established that the maximum of electron mobility in the channel 20 region is higher than the maximum of electron mobility in the channel region.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体装置，其可以降低功率耗散并提供用于对其进行制造的方法。解决方案：MISFET 10设置有具有杂质浓度C的沟道区20，形成在沟道区20上的SiO 2 绝缘膜11的p型衬底1和HfSiON 形成在绝缘膜11上的绝缘膜12.假设另一个MISFET，其具有杂质浓度C并且由与基板1相同的材料构成的基板和仅形成在沟道区上的由SiON构成的绝缘膜; 通道区域20的杂质浓度C被确定为使得通道20区域中的电子迁移率的最大值高于沟道区域中的电子迁移率的最大值。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2005303074A Thin film deposition equipment, and thin film forming method 审中-公开
标题翻译：薄膜沉积设备和薄膜成型方法
公开(公告)号：JP2005303074A
公开(公告)日：2005-10-27
申请号：JP2004118174
申请日：2004-04-13
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWASE KAZUMASA , UMEDA KOJI , INOUE MASAO
IPC分类号： C23C16/42 , H01L21/31 , H01L21/316
摘要： PROBLEM TO BE SOLVED: To provide a thin film deposition equipment and a thin film forming method which are used for performing densification of an insulating film at comparatively low temperature without oxidizing the region of a ground.
SOLUTION: In the thin film deposition equipment 50 in order to form a predetermined thin film by holding a semiconductor substrate 7; a reaction chamber 2, a stage 3, an infrared heating mechanism 11, a silane based gas leading port 8a, an oxidizing quality gas leading port 9a, a silane based gas supply source 8, an oxidizing quality gas supply source 9, an exhaust port 13, and a vacuum pump 15, are installed. Furthermore, in order to perform oxygen radical treatment to a silicon oxide film formed on the semiconductor substrate 7, a microwave generator 5, an antenna 4, an argon gas leading poat 10a, and an argon gas supply source 10 are installed. Plasma of argon is formed, oxygen is excited, and oxygen radical is generated.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种薄膜沉积设备和薄膜形成方法，其用于在相对低的温度下进行绝缘膜的致密化而不氧化地面的区域。解决方案：在薄膜沉积设备50中，为了通过保持半导体衬底7形成预定的薄膜; 反应室2，载物台3，红外线加热机构11，硅烷类气体导出口8a，氧化品气体导出口9a，硅烷系气体供给源8，氧化质量气体供给源9，排气口 13和真空泵15。此外，为了对形成在半导体衬底7上的氧化硅膜进行氧自由基处理，安装有微波发生器5，天线4，氩气引线焊条10a和氩气供给源10。形成氩等离子体，激发氧，产生氧自由基。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2010114310A Method of manufacturing semiconductor device, and semiconductor device 审中-公开
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2010114310A
公开(公告)日：2010-05-20
申请号：JP2008286578
申请日：2008-11-07
申请人： Panasonic Corp , Renesas Technology Corp , パナソニック株式会社 , 株式会社ルネサステクノロジ
发明人： YASUMA MASATOSHI , INOUE MASAO , SAKASHITA SHINSUKE , SATO YOSHIHIRO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/308 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an MIPS gate structure and prevented in diffusion of silicon from a polycrystalline silicon layer to a metal layer without forming a notch shape on the metal layer. SOLUTION: In the method of manufacturing the semiconductor device having an MIPS gate structure, a manufacturing process of an MIPS gate includes steps of: sequentially depositing, on a semiconductor substrate, a gate insulating film, a metal layer, and a polycrystalline silicon layer; etching the polycrystalline layer using an etching mask formed on the polycrystalline silicon layer; leaving the metal layer having a sidewall projected downward in a tapered form by selectively etching the metal layer; oxidizing a tapered part of a plated layer projected outward from a plane including the sidewall of the polycrystalline silicon layer to form an oxidized tapered part; and removing the oxidized tapered part by etching. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有MIPS栅极结构的半导体器件，并且防止硅从多晶硅层扩散到金属层，而不在金属层上形成切口形状。解决方案：在制造具有MIPS栅极结构的半导体器件的方法中，MIPS栅极的制造工艺包括以下步骤：在半导体衬底上依次沉积栅绝缘膜，金属层和多晶硅层; 使用形成在多晶硅层上的蚀刻掩模蚀刻多晶层; 通过选择性地蚀刻金属层而使金属层具有以锥形形式向下突出的侧壁; 氧化从包括多晶硅层的侧壁的平面向外突出的镀层的锥形部分，以形成氧化的锥形部分; 并通过蚀刻去除氧化的锥形部分。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2006313769A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006313769A
公开(公告)日：2006-11-16
申请号：JP2005134917
申请日：2005-05-06
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： TSUJIKAWA SHINPEI , AKAMATSU YASUHIKO , UMEDA KOJI , YOSHIGAMI JIRO , MIZUTANI SEIJI , INOUE MASAO , TSUCHIMOTO JUNICHI , NOMURA KOJI
IPC分类号： H01L27/092 , H01L21/283 , H01L21/8238
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of simultaneously realizing improvement of performance of an NMOS transistor in a CMOS transistor and maintenance of NBTI reliability of a PMOS transistor, and a manufacturing method thereof. SOLUTION: Photolithography is used to form a resist mask RM3 having an opening on an NMOS region on a silicon substrate 101, N 2 (nitrogen) ions of dose of 1×10 15 /cm 2 are implanted therefrom at an acceleration voltage of 15 kV, thereby introducing a nitrogen into the silicon substrate 101 of the NMOS region. After that, a silicon oxide film is formed by an oxidation method using an active oxygen, and then, active nitrogen processing is executed to convert the silicon oxide film into an SiON thin film, and SiON gate insulation films 103 and 104 are formed on the NMOS region and the PMOS region, respectively. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供能够同时实现CMOS晶体管中的NMOS晶体管的性能的提高并且保持PMOS晶体管的NBTI可靠性的半导体器件及其制造方法。解决方案：光刻用于形成在硅衬底101上的NMOS区上具有开口的抗蚀剂掩模RM3，剂量为1×10 15的氮（N 2）离子在15kV的加速电压下从其中注入 / cm 2 / SP>，从而将氮引入到NMOS区的硅衬底101中。之后，通过使用活性氧的氧化法形成氧化硅膜，然后进行活性氮处理以将氧化硅膜转换成SiON薄膜，并在其上形成SiON栅极绝缘膜103和104 NMOS区和PMOS区。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006245306A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2006245306A
公开(公告)日：2006-09-14
申请号：JP2005059225
申请日：2005-03-03
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SAKASHITA SHINSUKE , MORI KENICHI , YOSHIGAMI JIRO , INOUE MASAO
IPC分类号： H01L29/78 , C23C16/34 , H01L21/28 , H01L21/285 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for suppressing damage to a gate insulation film to reduce gate leakage current and having a gate electrode with a work function similar to that of p-type polysilicon. SOLUTION: The gate insulation film 3 is formed on a silicon substrate 1. A TiN film 4 is formed on the gate insulation film 3 by a CVD method at a temperature of 450°C or lower. The TiN film 4 is etched to form the gate electrode 5. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种制造半导体器件的方法，用于抑制栅极绝缘膜的损伤，以减少栅极漏电流并具有与p型多晶硅类似的功函数的栅电极。解决方案：栅极绝缘膜3形成在硅衬底1上。在450℃或更低的温度下，通过CVD法在栅极绝缘膜3上形成TiN膜4。蚀刻TiN膜4以形成栅极5.版权所有：（C）2006，JPO＆NCIPI

8. 发明专利

JP2004342722A Semiconductor device and method of manufacturing the same 审中-公开
公开(公告)号：JP2004342722A
公开(公告)日：2004-12-02
申请号：JP2003135433
申请日：2003-05-14
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MARUYAMA YOSHITERU , UMEDA KOJI , INOUE MASAO
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device using a PMOS and a method of manufacturing semiconductor device by which the instability of hot carrier resistances and negative bias temperatures are dissolved.
SOLUTION: The semiconductor device is provided with a gate electrode 3 which is formed on a semiconductor substrate 1 through a gate insulating film 2 and into which an impurity is injected, and side walls 5 formed on the side walls of the gate electrode 3. In the semiconductor device. In the device, a first nitrogen-containing layer 20 having a higher dielectric constant than the gate insulating film 2 has is provided between the insulating film 2 and gate electrode 3, and second nitrogen-containing layers 6 having higher dielectric constants than the side walls 5 have are provided at height positions lower than that of the gate insulating film 2 between the semiconductor substrate 1 and side walls 5.
COPYRIGHT: (C)2005,JPO&NCIPI

9. 发明专利

JP2010153489A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010153489A
公开(公告)日：2010-07-08
申请号：JP2008328244
申请日：2008-12-24
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KADOSHIMA MASARU , KAWAHARA TAKAAKI , INOUE MASAO , YOSHIGAMI JIRO
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device where fluctuation of threshold voltage of a gate electrode part is suppressed, and to provide a method of manufacturing the device. SOLUTION: In an element forming region 2, a P-HK film 6 and a metal film 8 for work function control are formed. In an element forming region 3, an N-HK film 7 and a metal film 9 for work function control are formed. A polysilicon film 10 and a nickel silicide film 11 are formed on the metal films 8 and 9. A boundary sidewall insulating film 5 is interposed between the P-HK film 7 and the N-HK film 6 in a mode where it is brought into contact with the P-HK film 7 and the N-HK film 6, and the insulating film is also interposed between the metal film 8 and the metal film 9 in a mode where it is brought into contact with the metal film 8 and the metal film 9. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供抑制栅电极部分的阈值电压的波动的半导体器件，并提供一种制造器件的方法。解决方案：在元件形成区域2中，形成用于功函数控制的P-HK膜6和金属膜8。在元件形成区域3中，形成用于功函数控制的N-HK膜7和金属膜9。在金属膜8和9上形成多晶硅膜10和硅化镍膜11.在P-HK膜7和N-HK膜6之间插入边界侧壁绝缘膜5，与P-HK膜7和N-HK膜6接触，绝缘膜也以金属膜8与金属膜8接触的方式插入在金属膜8和金属膜9之间电影9.版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2008218852A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2008218852A
公开(公告)日：2008-09-18
申请号：JP2007056650
申请日：2007-03-07
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HAYASHI TAKESHI , NISHIDA MASAO , INOUE MASAO , MIZUTANI SEIJI , SAKASHITA SHINSUKE , YOSHIGAMI JIRO
IPC分类号： H01L21/265 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device that can improve transistor characteristics when fluorine injection or nitrogen injection into a channel is performed. SOLUTION: A semiconductor substrate has n-type impurities selectively injected into an n-type well 13 for forming pMOS as channel doping (n-type impurity injection stage). Then the same mask for photoengraving with the n-type impurity injection stage is used to selectively inject fluorine into the n-type well 13 to a concentration of 1×10 15 /cm 2 to sufficiently lower a threshold. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种当执行氟注入或氮注入到通道中时可以提高晶体管特性的半导体器件的制造方法。解决方案：半导体衬底具有选择性地注入用于形成pMOS的n型阱13中的n型杂质作为沟道掺杂（n型杂质注入级）。然后使用与n型杂质注入级相同的掩模进行照相印刷，以便将n型阱13中的氟选择性地注入浓度为1×10 15 / SP / cm 2 / SP>以充分降低阈值。版权所有（C）2008，JPO＆INPIT

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