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41. 发明专利

JP2009170763A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009170763A
公开(公告)日：2009-07-30
申请号：JP2008009023
申请日：2008-01-18
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： FURUSAWA KENJI , KAMOSHIMA TAKAO , AJIRO YUUJI
IPC分类号： H01L21/60 , H01L21/3205 , H01L23/52
CPC分类号： H01L23/535 , H01L22/32 , H01L23/522 , H01L23/562 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05095 , H01L2224/05166 , H01L2224/05187 , H01L2224/05548 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/45015 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/20753 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： PROBLEM TO BE SOLVED: To suppress or prevent the generation of cracks in an insulating film below an external terminal due to the external force applied on the external terminal of a semiconductor device. SOLUTION: A plurality of wiring layers are formed on the main surface of a semiconductor substrate 1. In a fifth wiring layer M5, located immediately below the uppermost wiring layer MH among the plurality of wiring layers, a conductor pattern (a fifth wiring 5F, a terminal wiring and a plug 6C) is not formed immediately below the probe contacting region PA of a bonding pad PD for the uppermost wiring layer MH. In the fifth wiring layer M5, the conductor pattern (the fifth wiring 5F, the terminal wiring and the plug 6C) is formed in a region, other than the same, immediately below the probe contacting region PA of the bonding pad PD for the uppermost wiring layer MH. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了抑制或防止由于施加在半导体器件的外部端子上的外力而在外部端子下方的绝缘膜中产生裂纹。解决方案：在半导体衬底1的主表面上形成多个布线层。在第五布线层M5中，位于多个布线层中的最上布线层MH的正下方，导体图案（第五布线5F，端子布线和插塞6C）不形成在用于最上布线层MH的接合焊盘PD的探针接触区域PA的正下方。在第五布线层M5中，导体图案（第五布线5F，端子布线和插塞6C）形成在不同于其的区域的正下方的焊盘PD的探针接触区域PA的正下方接线层MH。版权所有（C）2009，JPO＆INPIT

43. 发明专利

JP2008258258A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008258258A
公开(公告)日：2008-10-23
申请号：JP2007096327
申请日：2007-04-02
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： MORIKAWA NARIHIRO , INABA YUICHI , GOTO YUJI
IPC分类号： H01L21/3205 , H01L23/52
CPC分类号： H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a structure capable of relieving mechanical stress to be applied to a bonding pad. SOLUTION: A third interlayer insulation film 13 provided with a via hole 12 is formed on a second interlayer insulation film 9 to cover a third wiring layer 11. A third conductive layer 14 is formed within the via hole 12. A plurality of pillar-shaped interlayer insulation films 13a in a hexagonal plane shape are gathered to form a third interlayer insulation film 13. The via hole 12 and the third conductive layer 14 are formed surrounding each of the pillar-shaped interlayer insulation films 13a. A fourth wiring layer 15 electrically connected to the third wiring layer 11 through the third conductive layer 14 is formed. In this embodiment, the fourth wiring layer 15 is an uppermost wiring layer and functions as a bonding pad. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供具有能够减轻施加到接合焊盘的机械应力的结构的半导体器件。解决方案：设置有通孔12的第三层间绝缘膜13形成在第二层间绝缘膜9上以覆盖第三布线层11.第三导电层14形成在通孔12内。多个聚集六边形平面形状的柱状层间绝缘膜13a以形成第三层间绝缘膜13.围绕每个柱状层间绝缘膜13a形成通孔12和第三导电层14。形成通过第三导电层14电连接到第三布线层11的第四布线层15。在本实施例中，第四布线层15是最上层布线层，起到焊盘的作用。版权所有（C）2009，JPO＆INPIT

44. 发明专利

JP2008177249A Bonding pad for semiconductor integrated circuit, manufacturing method for the bonding pad, semiconductor integrated circuit, and electronic equipment 审中-公开
标题翻译：用于半导体集成电路的接合焊盘，用于接合焊盘，半导体集成电路和电子设备的制造方法
公开(公告)号：JP2008177249A
公开(公告)日：2008-07-31
申请号：JP2007007492
申请日：2007-01-16
申请人： Sharp Corp , シャープ株式会社
发明人： ISHIHARA KAZUYA , AWAYA NOBUYOSHI
IPC分类号： H01L21/3205 , H01L21/60 , H01L23/52
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05006 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05558 , H01L2224/05567 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/451 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/05042 , H01L2924/14 , H01L2224/48 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable bonding pad for a semiconductor integrated circuit which ensures the flatness of the surface of the pad, allows conduction of a sufficient amount of current, and shows less conduction failure on an opening path interconnecting metal wiring layers.
SOLUTION: The bonding pad 10 for the semiconductor integrated circuit includes the opening path P interconnecting the metal wiring layers. The opening path P is composed of a latticed pattern of opening portions having at least two different opening widths consisting of one opening width necessary for filling the opening path and another opening width larger than one opening width.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种高可靠性的用于半导体集成电路的焊盘，其确保焊盘表面的平坦度，允许传导足够量的电流，并且在互连的开口路径上显示较少的导通故障金属布线层。解决方案：用于半导体集成电路的焊盘10包括互连金属布线层的开口路径P. 开口路径P由具有至少两个不同开口宽度的开口部分的网格图案组成，该开口宽度由填充开口路径所需的一个开口宽度和大于一个开口宽度的另一开口宽度组成。版权所有（C）2008，JPO＆INPIT

45. 发明专利

JP2007273624A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007273624A
公开(公告)日：2007-10-18
申请号：JP2006095737
申请日：2006-03-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SAITO NOBUKATSU , UNO TADASHI , KANO MASASHI , MATSUOKA YOSHIHIRO
IPC分类号： H01L21/3205 , H01L21/60 , H01L23/52
CPC分类号： H01L24/05 , H01L23/293 , H01L23/3192 , H01L24/03 , H01L24/13 , H01L2224/02166 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05012 , H01L2224/05086 , H01L2224/05095 , H01L2224/05124 , H01L2224/05571 , H01L2224/05573 , H01L2224/05666 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/131 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H01L2924/00014 , H01L2924/01014 , H01L2224/05552 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device inhibiting the peeling of a wiring layer and a conductive layer due to a thermal stress at a time when a semiconductor substrate is mounted, preventing an electrical disconnection and having a high performance and a high reliability and an efficient manufacturing method for the semiconductor device. SOLUTION: The semiconductor device has the semiconductor substrate (such as a silicon wafer 10), the wiring layer 14 formed on the semiconductor substrate 10 and a first conductive layer 15 formed on the wiring layer. The semiconductor device further has an inter-layer insulating film 16 formed on the first conductive layer and a second conductive layer 17 formed on the inter-layer insulating film 16 in a conductible manner with the first conductive layer 15. A bump is formed on the second conductive layer. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：为了提供一种半导体器件，其在安装半导体衬底时由于热应力而抑制布线层和导电层的剥离，防止电断开并具有高性能和高可靠性和半导体器件的高效制造方法。解决方案：半导体器件具有半导体衬底（例如硅晶片10），形成在半导体衬底10上的布线层14和形成在布线层上的第一导电层15。半导体器件还具有形成在第一导电层上的层间绝缘膜16和与第一导电层15以可导电的方式形成在层间绝缘膜16上的第二导电层17。第二导电层。版权所有（C）2008，JPO＆INPIT

46. 发明专利

JP2007027481A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007027481A
公开(公告)日：2007-02-01
申请号：JP2005208666
申请日：2005-07-19
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： YUZAWA TAKESHI , TAGAKI MASATOSHI
IPC分类号： H01L21/3205 , H01L23/52
CPC分类号： H01L27/088 , H01L21/823475 , H01L23/528 , H01L24/05 , H01L27/0203 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/19043 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device in which a semiconductor element can be provided below a pad.
SOLUTION: The semiconductor device includes a semiconductor layer 10 having element forming regions 10A, 10B; a first conductive layer provided above the semiconductor layer 10 and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; interlayer insulation layers 50, 60 provided above the semiconductor layer 10; an electrode pad 62 provided above the interlayer insulation layers 50, 60 and superimposed over the element forming region 10A in a plan view; and an element inhibition region 12 provided in a predetermined range positioned outward from a vertically lower portion of an end of at least one part of the electrode pad 62 in the semiconductor layer 10. In the element inhibition region 12, a connection portion in which the first and second conductive layers are connected is not arranged.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种高可靠性的半导体器件，其中半导体元件可以设置在焊盘的下方。解决方案：半导体器件包括具有元件形成区域10A，10B的半导体层10; 设置在半导体层10上方并具有第一宽度的第一导电层; 连接到所述第一导电层并且具有小于所述第一宽度的第二宽度的第二导电层; 设置在半导体层10上方的层间绝缘层50,60; 设置在层间绝缘层50,60之上并且在平面图中叠加在元件形成区域10A上的电极焊盘62; 以及设置在半导体层10中的电极焊盘62的至少一部分的端部的垂直下部的外侧的预定范围内的元件抑制区域12.在元件抑制区域12中，连接部分未布置第一和第二导电层。版权所有（C）2007，JPO＆INPIT

47. 发明专利

JP2007019128A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007019128A
公开(公告)日：2007-01-25
申请号：JP2005197043
申请日：2005-07-06
申请人： Sony Corp , ソニー株式会社
发明人： MIYAMORI YUUICHI
IPC分类号： H01L21/3205 , H01L21/60 , H01L23/52
CPC分类号： H01L24/05 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L24/03 , H01L2224/02166 , H01L2224/05006 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05166 , H01L2224/05181 , H01L2224/05553 , H01L2224/05567 , H01L2224/05571 , H01L2224/05624 , H01L2924/0002 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To reduce the effect of moisture that penetrates through the damage to an irreducible minimum so as to prevent moisture from penetrating into an interlayer insulating film where a circuit unit is formed even if damage, such as tissue etc, occurs in a pad. SOLUTION: A semiconductor device is equipped with: a pad 61 which is formed on multilayered wiring composed of the laminated wiring layers and interlayer insulating films and electrically connected to the outside. A second contact layer interlayer insulating film 43, a second wiring interlayer insulating film 33, and a first contact interlayer insulating film 23 provided under the pad 61, are surrounded with a moisture-resistant protective member 71 which is formed as continuously connected to the peripheral underside of the pad 61. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了将渗透损伤的水分的影响减小到不可约的最小值，以防止水分渗入形成电路单元的层间绝缘膜，即使是诸如组织等的损伤，发生在垫中。解决方案：半导体器件配备有：焊盘61，其形成在由层叠布线层和层间绝缘膜构成并与外部电连接的多层布线上。设置在焊盘61下方的第二接触层层间绝缘膜43，第二布线层间绝缘膜33和第一接触层间绝缘膜23被防潮保护构件71围绕，防潮保护构件71连续地连接到外围（P）版权所有（C）2007，JPO＆INPIT

48. 发明专利

JP2005223245A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005223245A
公开(公告)日：2005-08-18
申请号：JP2004031877
申请日：2004-02-09
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： MATSUBARA YOSHIHISA
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/44 , H01L21/768 , H01L23/48 , H01L23/485
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/05 , H01L24/10 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05095 , H01L2224/05124 , H01L2224/05548 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/05042 , H01L2924/19041 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having high mechanical strength and capable of reducing the size of a semiconductor chip.
SOLUTION: Protection elements, i.e. a diode 119 and a capacitive element, are formed on a silicon substrate 101 and a silicon oxide film 102 is formed to cover the protection elements. A low dielectric constant film 103 having mechanical strength lower than that of the silicon oxide film is formed on the silicon oxide film 102. In the low dielectric constant film 103 above the capacitive element, a power supply mesh structure consisting of power supply lines 116 and ground lines 115 for the protection elements is formed to also serve as a reinforcing structure of the low dielectric constant film 103.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有高机械强度并能够减小半导体芯片的尺寸的半导体器件。解决方案：在硅衬底101上形成保护元件，即二极管119和电容元件，并且形成氧化硅膜102以覆盖保护元件。在氧化硅膜102上形成机械强度低于氧化硅膜的低介电常数膜103.在电容元件上方的低介电常数膜103中，由电源线116和形成用于保护元件的接地线115也用作低介电常数膜103的增强结构。版权所有（C）2005，JPO＆NCIPI

49. 发明专利

JP2005116562A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005116562A
公开(公告)日：2005-04-28
申请号：JP2003344822
申请日：2003-10-02
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： TOMIMATSU TAKAHIRO
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is reduced in stress generated when a probe is brought into contact with the same.
SOLUTION: On a semiconductor substrate 1, undermetal 3 is formed. An interlayer insulation film 5 is so formed as to cover the undermetal 3. In the interlayer insulation film 5, an annular opening 5b is so formed as to surround part of the interlayer insulation film 5 located immediately above the undermetal 3 from the circumferential direction. In the annular opening 5b, a guard ring 8 is formed. In each of a plurality of openings 5a formed in part of the interlayer insulation film 5 located inside of the guard ring 8, a columnar tungsten 7 is formed. Above the part of the interlayer insulation film 5 located immediately above the undermetal 3, top metal 6 is formed. The guard ring 8 is so formed that the contour shape in a cross section parallel to a principal plane of the semiconductor substrate 1 may be nearly circle.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种当探头与其接触时产生的应力减小的半导体器件。解决方案：在半导体衬底1上形成下金属3。层间绝缘膜5被形成为覆盖下金属3。在层间绝缘膜5中，环形开口5b形成为围绕位于下金属3正上方的层间绝缘膜5的周向的一部分。在环形开口5b中形成保护环8。在形成在位于保护环8内部的层间绝缘膜5的一部分的多个开口部5a中，形成有柱状的钨7。在位于下金属3正上方的层间绝缘膜5的部分之上，形成顶部金属6。保护环8的形状使得与半导体基板1的主平面平行的截面中的轮廓形状可以接近圆形。版权所有（C）2005，JPO＆NCIPI

50. 发明专利

JP2005064218A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005064218A
公开(公告)日：2005-03-10
申请号：JP2003292052
申请日：2003-08-12
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： TAWA SHIGERO
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： H01L24/06 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05553 , H01L2224/05554 , H01L2224/45 , H01L2224/45015 , H01L2224/45144 , H01L2224/48 , H01L2224/48091 , H01L2224/48463 , H01L2224/48599 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/19043 , H01L2924/20754 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent the pad stripping, ball stripping, etc. from occurring in the bonding process without lowering the reliability due to the electromigration of metal wirings, etc. SOLUTION: A plurality of rectangular pads 10 are arranged on a semiconductor chip 100 along its four sides, an inner circuit region 20 is formed inside the plurality of pads 10 on the chip 100, and a passivation film 30 is formed on the chip 100 to protect other regions than the pads 10. The outer region (at the four sides of the chip 100) of the pad 10 is a probing square or similar region 11, the inner region (at the inner circuit region 20) is a bonding square or similar region 12, and the region between the probing region 11 and the bonding region 12 is a conduction region 13 for electrically conducting both regions. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止在接合过程中发生垫剥离，球剥离等，而不会降低由于金属布线的电迁移等导致的可靠性。解决方案：多个矩形垫10 沿着其四边布置在半导体芯片100上，在芯片100上的多个焊盘10的内侧形成有内部电路区域20，并且在芯片100上形成钝化膜30以保护与焊盘10不同的其它区域。焊盘10的外部区域（芯片100的四侧）是探测正方形或类似的区域11，内部区域（内部电路区域20）是接合方形或类似区域12，并且区域探测区域11和接合区域12是用于导电两个区域的导电区域13。版权所有（C）2005，JPO＆NCIPI

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