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41. 发明专利

JPH01251715A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01251715A
公开(公告)日：1989-10-06
申请号：JP7886688
申请日：1988-03-31
申请人： TOSHIBA CORP
发明人： YAMABE KIKUO , TSUNASHIMA YOSHITAKA , OKUMURA KATSUYA
IPC分类号： H01L21/22 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To form a uniform diffusion layer on the internal walls of a groove having vertical sidewalls by forming a first thin film and doping an impurity into a second thin film whose diffusion coefficient is greater than that of the first thin film and thereby using the impurity as a diffuser. CONSTITUTION:A groove 13 is formed by etching a p-type silicon substrate 11 on which an SiO2 film 12 has been deposited. After removing the SiO2 film 12 with diluted hydrofluoric acid, an SiO2 film 14 containing no impurity is deposited, e.g., 100nm thick over the entire surface and thereafter, a polycrystalline silicon film 15 is deposited, e.g., 100nm thereon. Then, an As ion is implanted at an angle of incidence 7 deg. inclined in the vertical direction with respect to the substrate surface with a doping amount of 10 /cm or greater at an accelerating voltage of 50kev. The substrate is subjected to a thermal treatment in an oxygen atmosphere to cause As within the polycrystalline silicon film 15 to diffuse over the substrate surface and to thereby form an n-type layer 16 on the internal walls of the groove 13. Accordingly, a desired n-type layer can be formed on the internal walls of a thin, deep capacitor groove without damaging the substrate.

42. 发明专利

JPH01242780A THIN FILM-FORMING EQUIPMENT AND METHOD FOR CLEANING SAME 失效
公开(公告)号：JPH01242780A
公开(公告)日：1989-09-27
申请号：JP7092388
申请日：1988-03-25
申请人： TOSHIBA CORP
发明人： TSUNASHIMA YOSHITAKA , MIYAZAKI SHINJI
IPC分类号： C23C16/50 , H01L21/205 , H01L21/31
摘要： PURPOSE:To remove deposits in a furnace by means of etching under optimum conditions by providing electrodes for producing plasma to the parts close to the connection of a reaction furnace with an exhaust system and removing the deposits in the furnace. CONSTITUTION:At the time of heating a substrate 1 in a reaction furnace and introducing a reactant gas to form a thin film, deposits 16, 15 are formed on the inner wall of the reaction furnace. In order to clean the inside of the reaction furnace, the inside of the reaction furnace is evacuated and the prescribed etching gas is introduced through a gas-introducing pipe 7. The introduced gas is formed into plasmic state in high-temp. and low-temp. regions by means of electrodes 8, 9, respectively, by which the deposits 16, 15 are gasified and removed. At this time, plasma may be independently produced respectively in high-temp. and low-temp. regions, and also activated etching gas may be used in the low-temp. region. By this method, the deposits in the furnace can be removed by means of etching under optimum conditions.

43. 发明专利

JPH01186615A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01186615A
公开(公告)日：1989-07-26
申请号：JP488388
申请日：1988-01-14
申请人： TOSHIBA CORP
发明人： KAWAGUCHI HIDEKAZU , TSUNASHIMA YOSHITAKA , YAMABE KIKUO , OKUMURA KATSUYA
IPC分类号： H01L21/225 , H01L21/205 , H01L21/822 , H01L27/04
摘要： PURPOSE:To raise an adsorption efficiency of an electric conductive layer formation element or a compound including an electric conductive layer formation element, by forming more than one atomic layer of a semiconductor atom made of the same material as that of a substrate on the surface of the semiconductor substrate, making the surface of the semiconductor substrate an active one to adsorption. CONSTITUTION:On the surface of a semiconductor substrate 1-1, more than one atomic layer of a semiconductor atom 1-3 made of the same material as that of the substrate is formed for formation of a semiconductor layer surface 1-4 having no natural oxide film 1-2. Next, an adsorption of an electric conductive layer (1-5) formation element or a compound including an electric conductive layer formation element is conducted. Since the natural oxide film 1-2 formed on the substrate surface avoids a adsorption of an impurity element or a compound including an impurity element, a uniform and good controllable impurity diffusion layer can be formed both on the flat and recessed areas.

44. 发明专利

JPS6474719A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6474719A
公开(公告)日：1989-03-20
申请号：JP23102287
申请日：1987-09-17
申请人： TOSHIBA CORP
发明人： YAMABE KIKUO , TSUNASHIMA YOSHITAKA
IPC分类号： H01L27/04 , H01L21/22 , H01L21/225 , H01L21/316 , H01L21/822
摘要： PURPOSE:To form a diffusion layer with good controllability, by once giving oxidation treatment to the silicon surface inside a groove followed by performing silicon oxidation treatment while adding impurities to the surface inside the groove. CONSTITUTION:An oxide film 2 to become a mask, when a groove is formed on a silicon substrate by reactive ion etching (RIE), is formed by CVD. After the oxide film of the groove formation part is removed by a photographic etching and by RIE of the oxide film 2, a groove 3 is formed by RIE. Subsequently, the oxide film 2 for the mask is removed by etching with dilluted hydrofluoric acid for forming the oxide film 4 above 20Angstrom with steam above 600 deg.C and treating it in a nonoxidation atmosphere of 1000 deg.C. Thereafter, the oxide film 4 is removed by etching with dilluted hydrofluoric acid, then being coated with the oxide film 5, to which arsenic atoms are added, by low pressure CVD followed by performing heat treatment in a nitrogen atmosphere of 1000 deg.C so as to form an impurities diffusion layer 6 on the groove surface.

45. 发明专利

JPS59132130A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59132130A
公开(公告)日：1984-07-30
申请号：JP531683
申请日：1983-01-18
申请人： Toshiba Corp
发明人： TSUNASHIMA YOSHITAKA
IPC分类号： H01L21/302 , H01L21/3065
CPC分类号： H01L21/302
摘要： PURPOSE:To etch a conductive film on a thin insulating film without the dielectric breakdown of the insulating film by etching the conductive film while irradiating beams of energy of an energy barrier or more of the interface between a substrate and the insulating film. CONSTITUTION:A field oxide film 2, a gate oxide film 3 and a phosphorus doped polycrystalline silicon film 4 are formed on a (100) face N type S substrate 1 in succession. A resist film 5 is formed on an element forming region. The phosphorus doped polycrystalline silicon film 4 is etched through reactive ion etching while the resist film 5 is used as a mask and beams of energy of an energy barrier or more of the Si substrate 1 and the gate oxide film 3 are irradiated, and a gate electrode 6 is formed. The resist film 5 is removed, and an MOS capacitor is manufactured.
摘要翻译：目的：通过蚀刻导电膜同时照射能量阻挡层的能量或基板和绝缘膜之间的界面的更多能量，来蚀刻绝缘薄膜上的导电膜而不会导致绝缘膜的电介质击穿。构成：在（100）面N型S基板1上依次形成场氧化膜2，栅极氧化膜3和磷掺杂多晶硅膜4。在元件形成区域上形成抗蚀剂膜5。通过反应离子蚀刻蚀刻磷掺杂多晶硅膜4，同时将抗蚀剂膜5用作掩模，照射Si衬底1和栅极氧化物膜3的能量势垒或更多的能量束，并且栅极形成电极6。除去抗蚀剂膜5，制造MOS电容器。

46. 发明专利

JP2012160737A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2012160737A
公开(公告)日：2012-08-23
申请号：JP2012051848
申请日：2012-03-08
申请人： Toshiba Corp , 株式会社東芝
发明人： TSUNASHIMA YOSHITAKA , SUGURO KYOICHI , IINUMA TOSHIHIKO , MATSUO KOJI , MURAKOSHI ATSUSHI
IPC分类号： H01L27/092 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that achieves microfabrication and ensures the reliability of, for example, a gate electrode.SOLUTION: In a gate formation region of each of an N-type MIS transistor and a P-type MIS transistor, a first metal-containing film F1 is formed on a gate insulating film F0 formed in a recess in the gate formation region of the N-type MIS transistor, and a third metal-containing film F3 is formed on the gate insulating film F0 formed in a recess of the gate formation region of the P-type MIS transistor. Second metal-containing films F2 are formed on the first metal-containing film F1 and the third metal-containing film F3. The work function of the first metal-containing film F1 contacting the gate insulating film F0 of the N-type MIS transistor is smaller than that of the third metal-containing film F3 contacting the gate insulating film F0 of the P-type MIS transistor.
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，其实现微细加工并确保例如栅电极的可靠性。解决方案：在N型MIS晶体管和P型MIS晶体管的栅极形成区域中，第一含金属膜F1形成在形成在栅极形成中的凹部中的栅极绝缘膜F0上 N型MIS晶体管的区域和形成在P型MIS晶体管的栅极形成区域的凹部中的栅极绝缘膜F0上形成第三含金属膜F3。第二含金属膜F2形成在第一含金属膜F1和第三含金属膜F3上。与N型MIS晶体管的栅极绝缘膜F0接触的第一含金属膜F1的功函数小于与P型MIS晶体管的栅极绝缘膜F0接触的第三含金属膜F3的功函数。版权所有（C）2012，JPO＆INPIT

47. 发明专利

JP2009099598A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009099598A
公开(公告)日：2009-05-07
申请号：JP2007266811
申请日：2007-10-12
申请人： Toshiba Corp , 株式会社東芝
发明人： ISHIDA KOICHI , SUZUKI TAKASHI , OZAWA YOSHIO , MIZUSHIMA ICHIRO , TSUNASHIMA YOSHITAKA
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/20 , H01L21/265 , H01L21/28 , H01L27/115 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/84 , H01L27/11524 , H01L27/1203
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing an accumulation of carriers in a single-crystal silicon layer.
SOLUTION: The semiconductor device comprises a single-crystal silicon substrate 11, an insulating layer 12 partially formed on the single-crystal silicon substrate, a single-crystal silicon layer 14 formed on the single-crystal silicon substrate and the insulating layer and including a defect layer based on an excessive group-IV element, a first gate insulating film 16 formed on the single-crystal silicon layer, and a plurality of first gate structure 31 for memory cell including: a charge storage layer 17 formed on the first gate insulating film; a second gate insulating film 19 formed on the charge storage layer; and a control gate electrode 22 formed on the second gate insulating film.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够防止载流子在单晶硅层中的积聚的半导体器件。解决方案：半导体器件包括单晶硅衬底11，部分地形成在单晶硅衬底上的绝缘层12，形成在单晶硅衬底上的单晶硅层14和绝缘层并且包括基于过量的IV族元件的缺陷层，形成在单晶硅层上的第一栅极绝缘膜16和用于存储单元的多个第一栅极结构31，包括：形成在第一栅极绝缘膜16上的电荷存储层17 第一栅绝缘膜; 形成在电荷存储层上的第二栅极绝缘膜19; 以及形成在第二栅极绝缘膜上的控制栅电极22。版权所有（C）2009，JPO＆INPIT

48. 发明专利

JP2008258635A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008258635A
公开(公告)日：2008-10-23
申请号：JP2008105170
申请日：2008-04-14
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGURO KYOICHI , MIYANO KIYOTAKA , MIZUSHIMA ICHIRO , TSUNASHIMA YOSHITAKA , HIRAOKA TAKAYUKI , ARIKADO TSUNETOSHI
IPC分类号： H01L21/76 , H01L21/20 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which comprises an MOS type element in which a variation in element characteristic is controlled.
SOLUTION: The semiconductor devices is provided with an element isolation insulating film which is embedded in a semiconductor region of a substrate; a semiconductor layer of the semiconductor region in which elements are separated by the element isolation insulating film, and an upper portion of the semiconductor layer projects above the surface of the element isolation insulating film; an MOS type element in which a source-drain region, a gate insulating film and a gate electrode are formed in the semiconductor layer, and the gate electrode is formed on the element isolation insulating film in the section of a surface parallel to the direction of the width of a channel. The position of the upper surface of the semiconductor layer under the gate electrodes 20 nm or more higher than the position of the upper surface of the element isolation insulating film under the gate electrode.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种包括其元件特性变化被控制的MOS型元件的半导体器件。解决方案：半导体器件设置有元件隔离绝缘膜，其被嵌入在衬底的半导体区域中; 半导体区域的半导体层，其中元件被元件隔离绝缘膜分离，并且半导体层的上部突出在元件隔离绝缘膜的表面之上; 在半导体层中形成源极 - 漏极区域，栅极绝缘膜和栅电极的MOS型元件，并且栅极电极形成在元件隔离绝缘膜上的与通道的宽度。栅电极下方的半导体层的上表面的位置比栅电极下的元件隔离绝缘膜的上表面的位置高20nm以上。版权所有（C）2009，JPO＆INPIT

49. 发明专利

JP2005166929A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005166929A
公开(公告)日：2005-06-23
申请号：JP2003403283
申请日：2003-12-02
申请人： Toshiba Corp , 株式会社東芝
发明人： SEKINE KATSUYUKI , TSUNASHIMA YOSHITAKA , INUMIYA SEIJI , KANEKO AKIO , SATO MOTOYUKI , EGUCHI KAZUHIRO
IPC分类号： H01L21/316 , H01L21/314 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31645 , H01L29/518
摘要： PROBLEM TO BE SOLVED: To provide a method for forming an insulating film with a reliability.
SOLUTION: A silicate film 12 containing a metal (e.g., hafnium) is formed on a silicon substrate 10. Subsequently, the silicon substrate 10 is subjected to a heat treatment in an ND
3 gas atmosphere, whereby nitrogen (N) and heavy hydrogen (D) are introduced into a silicate film 12. Heavy hydrogen (D) is introduced into the silicate film 12 in place of hydrogen (H), whereby a reliability of the silicate film 12 is enhanced.
COPYRIGHT: (C)2005,JPO&NCIPI

50. 发明专利

JP2005158998A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2005158998A
公开(公告)日：2005-06-16
申请号：JP2003395307
申请日：2003-11-26
申请人： Toshiba Corp , 株式会社東芝
发明人： INUMIYA SEIJI , KANEKO AKIO , SATO MOTOYUKI , SEKINE KATSUYUKI , EGUCHI KAZUHIRO , TSUNASHIMA YOSHITAKA
IPC分类号： H01L29/423 , H01L21/316 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/6656 , H01L21/28202 , H01L21/823828 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for realizing a high performance semiconductor device with low power consumption by restraining an abnormal shift of flat band voltage in a MOS transistor, which employs a high dielectric insulating film such as a hafnium silicate film as a gate insulating film and a polycrystalline silicon (or silicon and germanium) film as a gate electrode.
SOLUTION: A silicon film or the like which serves as at least a part of a gate electrode 4 is formed on the gate insulating film 3, and thereafter a nitriding layer 5 or an oxidation layer is formed on an electrode/insulating film interface by annealing the silicon film or the like in a nitriding atmosphere like NO gas and NH
3 gas or in an oxidizing atmosphere like O
2 gas. Further, a silicon film which serves as at least a part of the gate electrode is formed on the gate insulating film, into which any of oxygen, fluorine, and carbon is in turn introduced. A resultant sample is annealed to form any of a nitriding layer, an oxidation layer, a fluorinating layer, and a carbonizing layer on a gate electrode/gate insulating film interface.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种通过抑制MOS晶体管中的平坦带电压的异常移位来实现低功耗的高性能半导体器件的制造方法，MOS晶体管采用高介电绝缘膜，例如硅酸铪作为栅极绝缘膜的膜和作为栅电极的多晶硅（或硅和锗）膜。解决方案：在栅极绝缘膜3上形成用作至少一部分栅电极4的硅膜等，然后在电极/绝缘膜上形成氮化层5或氧化层通过在诸如NO气体和NH 3 SB气体的氮化气氛中或在诸如O 2 SB气体的氧化气氛中退火硅膜等。此外，在栅绝缘膜上形成用作至少一部分栅电极的硅膜，其中导入氧，氟和碳中的任一个。将所得样品退火以在栅极/栅极绝缘膜界面上形成氮化层，氧化层，氟化层和碳化层中的任一种。版权所有（C）2005，JPO＆NCIPI

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