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41. 发明专利

JP2545904B2 失效
公开(公告)号：JP2545904B2
公开(公告)日：1996-10-23
申请号：JP33269087
申请日：1987-12-29
申请人： NIPPON DENSO CO
发明人： KUROYANAGI AKIRA , FUNAHASHI TOMOHIRO , FUJII TETSUO
IPC分类号： C30B29/06 , H01L21/20 , H01L21/336 , H01L27/00 , H01L29/78 , H01L29/786

42. 发明专利

JPH06132473A HYBRID IC 失效
公开(公告)号：JPH06132473A
公开(公告)日：1994-05-13
申请号：JP28275192
申请日：1992-10-21
申请人： NIPPON DENSO CO , ANDEN CO LTD
发明人： ISHIKAWA FUKUO , FUJII TETSUO , ISHIDA TOSHIO , IKEMOTO HIDEYUKI
IPC分类号： H01L25/18 , H01L25/04 , H05K1/05 , H05K1/18 , H05K3/28
摘要： PURPOSE:To allow adjustment and inspection of circuit prior to molding while satisfying both sufficient heat dissipation and low cost. CONSTITUTION:A plurality of leads 32 and a wiring pattern 33 are formed of a conductor pattern on the top surface of a metal board 31 through a dielectric film. Circuit elements, e.g. a power, IC, are mounted on the metal board 31 and connected through wire bonding or a conductive adhesive with the wiring pattern 33. Adjustment and inspection of circuit are then carried out by conducting the leads 32, and a circuit part 31a mounting various circuit elements is molded with molding resin 38 while projecting a terminal part 31b formed with the leads 32 from the molding resin 38. Since the metal board 31 serves as a heat plate, conventional heat sink or ceramic board is not required.

43. 发明专利

JPH04370980A SEMICONDUCTOR PRESSURE SENSOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH04370980A
公开(公告)日：1992-12-24
申请号：JP14759491
申请日：1991-06-19
申请人： NIPPON DENSO CO
发明人： FUJII TETSUO , GOTO YOSHITAKA
IPC分类号： G01L1/18 , G01L9/00 , G01L9/04 , H01L29/84
摘要： PURPOSE:To provide a semiconductor pressure sensor in which pressure sensitive elements can be arranged properly within one chip. CONSTITUTION:Thin wall parts 15 and 16 are formed as band-like in a part of silicon wafer, and at the same time a plurality of thin-wall diaphragm sections 17 and 18 are formed in a succeeding mounting direction on the sections 15 and 16, where piezo resistance layers are arranged.

44. 发明专利

JPH0446784B2 失效
公开(公告)号：JPH0446784B2
公开(公告)日：1992-07-31
申请号：JP120882
申请日：1982-01-06
申请人： NIPPON DENSO CO
发明人： FUJII TETSUO , SONOBE TOSHIO , YOSHINO YOSHI
IPC分类号： B60S1/08 , G01W1/14

45. 发明专利

JPH03112168A SEMICONDUCTOR PIEZOSENSOR 失效
公开(公告)号：JPH03112168A
公开(公告)日：1991-05-13
申请号：JP25034489
申请日：1989-09-26
申请人： NIPPON DENSO CO
发明人： GOTO YOSHITAKA , FUJII TETSUO
IPC分类号： G01L9/04 , G01L9/00 , H01L29/84
摘要： PURPOSE:To obtain a semiconductor piezosensor whose dynamic range is wide and whose linearity is excellent by a method wherein a first semiconductor strain element and a second semiconductor strain element are installed respectively at a first strain- causing part and a second strain-causing part and they are operated according to a bend, of the strain-causing parts, corresponding to a strain-causing force. CONSTITUTION:A first strain-causing part 22 is formed to be thinner than a second strain-causing bart 24; only the strain-causing part 22 is bent mainly in a range of a low pressure; first semiconductor strain elements 31 installed at the strain-causing part 22 generate an output signal voltage whose sensitivity is high and whose linearity is good (change of resistance). When a bend of the strain-causing part 22 reaches a prescribed level, a first protruding stopper part 23 comes into contact with a shallow groove part 13 in a silicon wafer 1 and prevents an excessive bend of the strain-causing part 22 against a further increase in a pressure. Against the increase in the pressure after that, the strain-causing part 24 is bent by making use of the stopper part 23 as a support end. When a bend of the strain-causing part 24 reaches the prescribed level, a second stopper part 27 comes into contact with a deep groove part 12 in the silicon wafer 1 and prevents an excessive bend of the strain-causing part 24 against a further increase in the pressure.

46. 发明专利

JPH0367177A SEMICONDUCTOR ACCELERATION SENSOR 失效
公开(公告)号：JPH0367177A
公开(公告)日：1991-03-22
申请号：JP20418789
申请日：1989-08-07
申请人： NIPPON DENSO CO
发明人： FUJII TETSUO
IPC分类号： G01P15/12 , H01L21/302 , H01L21/3065
摘要： PURPOSE:To prevent the destruction of a movable part when excessive acceleration is impressed by bonding a semiconductor chip on a pedestal through a bump in a state where the movable part of the semiconductor chip is opposed to the pedestal. CONSTITUTION:The movable part is constituted of a beam part 12 having a piezoresistance layer 4 and an overlap part 13 on one side of the semiconductor chip. The semiconductor chip is bonded on a silicon substrate 15 through the bumps 9 and 19 with specified height in a state where the movable part is opposed to the substrate 15. According to the piezo-electric effect of the resistance 4 by the acceleration when the acceleration is impressed, a signal in accordance with the magnitude of the impressed acceleration is transmitted to the IC circuit of the substrate 15 through the bumps 9 and 19 and outputted to the outside from an electrode part 18 after performing processing for the signal such as amplification. In the case of impressing the excessive acceleration, a stopper functions to the movable part up and down, from right to left and back and forth, thereby preventing the destruction of the movable part.

47. 发明专利

JPH02194558A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02194558A
公开(公告)日：1990-08-01
申请号：JP1262889
申请日：1989-01-21
申请人： NIPPON DENSO CO
发明人： FUNAHASHI TOMOHIRO , FUJII TETSUO
IPC分类号： H01L27/146
摘要： PURPOSE:To make this device small and to set a highly efficient light detection sensitivity by a method wherein a metal wiring layer is formed on a p-n junction, a substrate main body is formed, the other substrate is bonded via an insulating layer, the other face of a semiconductor substrate is polished up to a part near the p-n junction and a light input is obtained. CONSTITUTION:An interlayer insulating layer 16 by, e.g. BPSG or the like is formed on the whole surface of a silicon substrate 11. Contact holes are formed in this insulating layer 16 so as to correspond to n regions 14a,14b,... and p regions 15a, 15b,...; a metal wiring layer 17 by aluminum is formed. This wiring layer is formed to be a prescribed pattern by, e.g. an etching process. An interlayer insulating film 18 is formed additionally on the interlayer insulating film 16 in which the wiring layer 17 has been formed; its face is made smooth; a substrate main body part 19 is constituted. The other face of the silicon substrate 11 is polished and is made thin in a state that a semiconductor substrate 20 has been bonded and that a reinforcement member has been formed. During this process, a range to be polished is up to a part of a LOCOS oxide film 12.

48. 发明专利

JPH0210577B2 失效
公开(公告)号：JPH0210577B2
公开(公告)日：1990-03-08
申请号：JP2915582
申请日：1982-02-25
申请人： NIPPON DENSO CO
发明人： MORITA NOBUKIO , FUJII TETSUO
IPC分类号： H01L23/522 , H01L21/31 , H01L21/768

49. 发明专利

JPH0258324A MANUFACTURE OF MULTILAYER SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0258324A
公开(公告)日：1990-02-27
申请号：JP21002188
申请日：1988-08-24
申请人： NIPPON DENSO CO
发明人： MAEDA HIROSHI , FUJII TETSUO
IPC分类号： H01L21/20 , H01L21/263 , H01L27/00
摘要： PURPOSE:To flatten an upper single crystal semiconductor layer by covering a part corresponding to the seed region of the surface of a lower single crystal silicon layer with a mask pattern, diffusing impurity except the seed region to make it porous, performing selective oxidization to form an oxide film layer, and then removing pattern. CONSTITUTION:Impurity is diffused on the surface of a lower semiconductor layer 21 except a part to be of a seed region to make the impurity diffused region selectively porous, for example, by an electrochemical reaction. When it is made porous in this manner, a part 26 becomes a state to be more easily oxidized than the other part, and an oxide film layer 27 is formed on a part except the seed region on the surface of the layer 21. That is, an insulating film layer is formed on the surface of the semiconductor layer in a flat state with the exposed part of the layer 21 to be of the seed region, and a single crystal semiconductor layer is formed thereon thereby to form an upper flat single crystal semiconductor layer 28 is indispensable formed, and a semiconductor circuit network is integrated with the whole surface of the upper semiconductor layer.

50. 发明专利

JPH0256918A DIRECT JOINT OF SEMICONDUCTOR WAFER 失效
公开(公告)号：JPH0256918A
公开(公告)日：1990-02-26
申请号：JP7783289
申请日：1989-03-28
申请人： NIPPON DENSO CO
发明人： GOTO YOSHITAKA , FUJII TETSUO , AZEYANAGI SUSUMU
IPC分类号： H01L21/762 , H01L21/02 , H01L21/76 , H01L27/12
摘要： PURPOSE:To suppress the creation of voids in the contact boundary between semiconductor wafers by a method wherein warping material films having a thermal expansion coefficient different from that of the wafers are formed on the one side surfaces of the respective wafers and, while the wafers are warped in an atmosphere whose temperature is different from that of the process for forming the warping material films, the whole contact surfaces of both the wafers are brought into contact with each other and the wafers are jointed by applying a current to the wafers. CONSTITUTION:Thermal silicon oxide films 2 and 5 having a thermal expansion coefficient different from that of silicon wafers 1 and 4 to be jointed are formed on one side surfaces of the silicon wafers 1 and 4. While both the silicon wafers 1 and 4 are warped in an atmosphere whose temperature is different from the temperature of the process for forming the oxide films 2, both the silicon wafers 1 and 4 are gradually brought into contact with each other until the contact surfaces are spread over the whole surfaces of the silicon wafers 1 and 4. While the whole areas of the contact surfaces of both the silicon wafers 1 and 4 are brought into contact with each other, SiO2/SiO2 of both the silicon wafers 1 and 4 are directly jointed. Therefore, the contact regions of the silicon wafers 1 and 4 are spread from the center point toward the circumference. With this constitution, the creation of non- contact parts (voids) between the silicon wafers 1 and 4 can be suppressed.

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