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    • 42. 发明专利
    • Device for forming thermal silicon nitride film
    • 形成硅氮化硅膜的装置
    • JPS58194718A
    • 1983-11-12
    • JP7489182
    • 1982-05-04
    • Nec Corp
    • BABA TOSHIO
    • C23C16/34C01B21/068H01L21/31H01L21/318H01L21/471
    • PURPOSE: The titled device capable of forming a uniform and relatively thick nitride silicon film, having constitution to heat only a silicon wafer and a suscepter in a reaction tube and to jet a nitrating gas from gas inlet set in the vicinity of the silicon wafer.
      CONSTITUTION: In a device for forming a thermally silicon nitride film, which is provided with the heater 71 such as infrared lamp, etc. to heat only the suscepter 2 and the silicon wafer 1 in the reaction tube 31 having the cover 5 equipped with the exhaust pipe 6 and the gas feed pipe 41 having a gas outlet positioned in the vicinity of the surface of the silicon wafer 1 at one end and connected to the source of the feed gas at the other end, the silicon wafer 1 is heated to the fixed temperature in an inert gas atmosphere, and a nitrating gas such as NH
      3 , etc. is fed from the feed pipe 41 to the device. The gas is sent without being decomposed until decomposed first above the wafer 1 surface, and permeated through the wafer 1 surface to form a relatively thick Si
      3 N
      4 film.
      COPYRIGHT: (C)1983,JPO&Japio
    • 目的:能够形成均匀且相对较厚的氮化硅膜的标题装置,其具有仅在硅晶片中加热的反应管的构造,并且在反应管中喷射来自设置在硅晶片附近的气体入口的硝化气体。 构成:在具有加热器71(例如红外线灯等)的热氮化硅膜的形成装置中,仅在具有盖5的反应管31中加热备用器2和硅晶片1, 排气管6和气体出口管41的一端具有位于硅晶片1的表面附近的气体出口,并且在另一端连接到进料气体源,将硅晶片1加热至 在惰性气体气氛中固定温度,并且从进料管41将诸如NH 3等硝化气体供给到该装置。 气体在不分解的情况下被送出,直到在晶片1表面之上首先分解,并透过晶片1表面形成较厚的Si 3 N 4膜。
    • 44. 发明专利
    • TUNNEL TRANSISTOR
    • JPH08186273A
    • 1996-07-16
    • JP33912694
    • 1994-12-28
    • NEC CORP
    • UEMURA TETSUYABABA TOSHIO
    • H01L29/68H01L29/205H01L29/80
    • PURPOSE: To provide a tunnel transistor suitable for finer form and has low voltage operation, high current density, and differential negative resistance. CONSTITUTION: On a semiinsulation GaAs substrate 1, an i-Al0.5 Ga0.5 As layer 2 and an i-GaAs layer 2a are laminated as intermediate buffer layers, and on top of them, p -GaAs 4 acting as drain and n -GaAs 5 acting as source are respectively formed. Between the source and drain, a lamination structure consisting of an n -GaAs layer 6 acting as channel and i-Al0.5 Ga0.5 As 7 acting as a gate insulation layer is formed, and on the source and drain, ohmic electrodes 8 and 9 are provided, and on the gate insulation layer, a Schottky electrode 10 is provided. And, the channel layer 6 directly doped is inserted, so that, in the state where voltage is not applied to the gate, high concentration electrons are induced, for increased tunnel current density and reduced gate leak current.
    • 48. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPH0541497A
    • 1993-02-19
    • JP19631991
    • 1991-08-06
    • NEC CORP
    • BABA TOSHIO
    • H01L27/092H01L21/8238
    • PURPOSE:To realize an inverter circuit having a small area with single element by using a degenerated semiconductor for the semiconductor forming a drain and commonly using a gate electrode for both an n- and p-channel MOS transistors by bringing the drains of the MOS transistors into contact with each other. CONSTITUTION:Si, n-Si, and p-Si are respectively used for forming a substrate 1, first semiconductor 2, and second semiconductor 3. In addition, n -Si, p -Si, and n-Si are respectively used form forming the third semiconductor 4, fourth semiconductor 5, and fifth semiconductor 6. Moreover, p-Si, SiO2, and Al are respectively used for forming the fifth sixth semiconductor 7, insulating film 8, and gate electrode 9, first electrode 10, second electrode 11, and third electrode 12. This semiconductor device has a laminated structure composed of an n-and p-channel MOS transistors and a tunnel junction formed of degenerated transistors is used for the junction between the third and fourth transistors. Therefore, the conventional MOS inverter circuit which is constituted by combining two transistors of different conductivity types can be realized by using this device only.
    • 50. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPS6247157A
    • 1987-02-28
    • JP18670185
    • 1985-08-27
    • NEC CORP
    • BABA TOSHIO
    • H01L29/205H01L21/331H01L29/20H01L29/73H01L29/737
    • PURPOSE:To obtain a semiconductor device of ultrahigh speed operation by laminating a P-type base layer, an I-type emitter depletion layer and an N-type contracted emitter layer on an N-type collector. CONSTITUTION:An N type collector 2, a P-type base 3, an I-type emitter 8 and a contracted N-type emitter 9 are epitaxially formed of the same GaAs on an N type GaAs substrate 1 by an MBE method. An AuGe/Au emitter electrode 7 is attached, an NEu+ type layer 9 is etched, an AuZn base electrode 6 is attached, an In collector electrode 5 is attached to the back surface, and alloyed in H2. Since no hetero boundary is provided, a problem of carrier recombination can be avoided, and the emitter and the base are low resistance and suppressed from generating a parasitic resistance. Since layer 6 is contracted, it operates as the emitter layer having wider forbidden band width than the base layer 3, and since the layer 8 has almost no ionized impurity, the diffusion constant and the mobility of the carrier are large to facilitate a high speed operation.