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41. 发明专利

JP2005332941A Complex and method for manufacturing complex and multilayer component 有权
标题翻译：用于制造复合物和多层组分的复合物和方法
公开(公告)号：JP2005332941A
公开(公告)日：2005-12-02
申请号：JP2004149287
申请日：2004-05-19
申请人： Kyocera Corp , 京セラ株式会社
发明人： KIMURA TETSUYA , FUKAMIZU NORIMITSU , YAMAMOTO KOJI , IRYO TSUTAE
IPC分类号： H01F41/04 , H01F17/00 , H05K1/02 , H05K3/10 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a complex and a method for manufacturing a complex and a method for manufacturing multilayer components for highly precisely forming a conductor without generating any bleeding or tapering. SOLUTION: On the main surface of a supporting plate 21 formed with a hydrophilic part 23a and a hydrophobic part 23b on at least one main surface, a conductor 29a containing at least metal powder is formed on the surface of one of the hydrophilic part 23a and the hydrophobic part 23b. A ceramic body 37a containing at least inorganic powder is formed in any region other than the region where the conductor 29a is formed, and the width of the conductor 29a at the supporting plate 21 side is set so as to be wider than the width of the conductor 29a at the opposite side of the supporting plate 21. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于制造复合物的复合物和方法以及用于制造用于高精度地形成导体的多层部件的方法，而不产生任何渗色或锥形化。解决方案：在至少一个主表面上形成有亲水部分23a和疏水部分23b的支撑板21的主表面上，至少包含金属粉末的导体29a形成在一个亲水部分部分23a和疏水部分23b。在除了形成导体29a的区域以外的任何区域中形成至少含有无机粉末的陶瓷体37a，并且将支撑板21侧的导体29a的宽度设定为宽于导体29a在支撑板21的相对侧。版权所有（C）2006，JPO＆NCIPI

42. 发明专利

JP2005217053A Composite sheet and composite part, laminated part, and method for manufacturing the same 审中-公开
标题翻译：复合片和复合部件，层压部件及其制造方法
公开(公告)号：JP2005217053A
公开(公告)日：2005-08-11
申请号：JP2004020283
申请日：2004-01-28
申请人： Kyocera Corp , 京セラ株式会社
发明人： YAMAMOTO KOJI , FUKAMIZU NORIMITSU , TATENO SHUICHI , KIMURA TETSUYA
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a composite sheet, a composite part, and a laminated part, wherein delamination occurrence is suppressed in the laminate of thin-layer green sheets for improvement on wiring board reliability, and to provide a method for manufacturing them.
SOLUTION: In this composite sheet A, a conductor pattern layer 7a thinner than an optically transparent ceramic green sheet 1a, and a photosetting ceramic layer 9a, are formed on the main surface of the optically transparent ceramic green sheet 1a with a through hole 3 therein filled up with a via conductor 5a. The conductor pattern layer 7a and the photosetting ceramic layer 9a are similar to each other in thickness, and the main surfaces of the conductor pattern layer 7a and the photosetting ceramic layer 9a are roughly flush with each other on the same plane.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供复合片材，复合部件和层压部件，其中薄层生片层压体中的分层发生被抑制以提高布线板的可靠性，并且提供一种方法制造他们。解决方案：在该复合片材A中，在光学透明陶瓷生片1a的主表面上形成具有比光学透明陶瓷生片1a更薄的导体图案层7a和光固化陶瓷层9a，孔3中填充有通孔导体5a。导体图案层7a和光固化陶瓷层9a的厚度彼此相似，并且导体图案层7a和光固化陶瓷层9a的主表面在同一平面上大致相互齐平。版权所有（C）2005，JPO＆NCIPI

43. 发明专利

JP2005159039A Circuit-forming laminate and circuit board 审中-公开
标题翻译：电路成型层压板和电路板
公开(公告)号：JP2005159039A
公开(公告)日：2005-06-16
申请号：JP2003396128
申请日：2003-11-26
申请人： Kyocera Corp , 京セラ株式会社
发明人： YAMAMOTO KOJI , FUKAMIZU NORIMITSU , TATENO SHUICHI , KIMURA TETSUYA
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a circuit forming laminated body which can simultaneously satisfy reduction of the thickness of an insulating layer and increase in the thickness of a wiring conductive layer, and to provide a circuit part using the same.
SOLUTION: A first composite sheet A, a second composite sheet B, and a third composite sheet C are laminated for calcining. The first composite sheet A, having a thickness of 50 μm or smaller, is such that a conductive pattern layer 3a is formed in a ceramic layer 2a, containing at least a ceramic material and an organic binder by penetrating the ceramic layer 2a; the second composite sheet B, having a thickness larger than 50 μm comprises a via conductor 5, in which a conductive paste containing a metal powder is filled in a through hole in a ceramic layer 2b containing at least the ceramic material and the organic binder; and the third composite sheet C, having a thickness of 50 μm or smaller is such that a functional pattern layer 12 is formed in a ceramic layer 2c, containing at least the ceramic material and the organic binder, if required, by penetrating the ceramic layer 2c.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种电路形成层叠体，其可以同时满足绝缘层的厚度的减小和增加布线导电层的厚度，并且提供使用其的电路部件。解决方案：将第一复合片材A，第二复合片材B和第三复合片材C层压以进行煅烧。厚度为50μm以下的第一复合片材A通过穿透陶瓷层2a而在至少含有陶瓷材料和有机粘合剂的陶瓷层2a中形成导电图案层3a，厚度大于50μm的第二复合片材B包括通孔导体5，其中将含有金属粉末的导电膏填充在至少包含陶瓷材料和有机粘合剂的陶瓷层2b的通孔中; 而第三复合片材C的厚度为50μm以下，在陶瓷层2c中形成功能图案层12，至少含有陶瓷材料和有机粘合剂，如果需要，通过穿透陶瓷层 2C。版权所有（C）2005，JPO＆NCIPI

44. 发明专利

JP2004235346A Manufacturing method of multilayer wiring board 审中-公开
标题翻译：多层布线板的制造方法
公开(公告)号：JP2004235346A
公开(公告)日：2004-08-19
申请号：JP2003020862
申请日：2003-01-29
申请人： Kyocera Corp , 京セラ株式会社
发明人： KIMURA TETSUYA , TAMI YASUHIDE , HAMANO SATOSHI , SHIGEOKA TOSHIAKI
IPC分类号： C04B35/64 , H01L23/12 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer wiring board of fine wiring, low resistance, and high dimensional precision. SOLUTION: A wiring circuit layer 3 is formed on the surface of a ceramic green sheet, and the green sheets 1 are laminated in a plurality of numbers. After a restrictive sheet 5 whose main component is the ceramic material which is hard to be sintered is laminated at least on one surface of the laminate, the laminate is sintered at or below the temperature of the melting point of the wiring circuit layer. The restrictive sheet 5 is removed by blasting the compressed air containing water-soluble abrasive particles. COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供一种精细布线，低电阻和高尺寸精度的多层布线板的制造方法。解决方案：在陶瓷生片的表面上形成布线电路层3，并且生片1以多个层叠。在主要成分是难以烧结的陶瓷材料的限制性片材5之间层叠在层叠体的至少一个表面上之后，层叠体在布线电路层的熔点或以下的温度下烧结。通过喷射含有水溶性磨料颗粒的压缩空气除去限制片5。版权所有（C）2004，JPO＆NCIPI

45. 发明专利

JP2004165601A Conductive paste composition and manufacturing methods of multi-level interconnection substrate which uses the same 审中-公开
公开(公告)号：JP2004165601A
公开(公告)日：2004-06-10
申请号：JP2003083763
申请日：2003-03-25
申请人： Kyocera Corp , 京セラ株式会社
发明人： FURUKUBO YOJI , SHIGEOKA TOSHIAKI , TAMI YASUHIDE , KIMURA TETSUYA , HAMANO SATOSHI
IPC分类号： H05K3/40 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a copper paste composition for forming a via conductor, superior in thermal decomposition characteristics for an organic binder and superior in adhesion properties with an interconnection circuit layer, such as a metal foil, and to provide a multi-level interconnection substrate which uses the composition. SOLUTION: A metal foil is bonded on a surface of a specified copy base 13 and is worked into a prescribed circuit pattern, to form the interconnection circuit layer 15. A through-hole, formed in a prescribed ceramic green sheet 11, is filled with a conductive paste containing a low-resistor metal to form a via conductor 12. The interconnection circuit layer 15, on the surface of the copy base 13 is transferred to the green sheet 11 for calcination. In this case, the conductive paste comprises low-resistor metal powder, the organic binder and a solvent, and 20-100 mass% organic binder contains nitrocellulose by, and 0-80 mass% methacrylic resin and acrylic resin. COPYRIGHT: (C)2004,JPO

46. 发明专利

JP2003163456A METHOD FOR MANUFACTURING MULTILAYER WIRING BOARD 审中-公开
公开(公告)号：JP2003163456A
公开(公告)日：2003-06-06
申请号：JP2001363635
申请日：2001-11-29
申请人： KYOCERA CORP
发明人： SHIGEOKA TOSHIAKI , HAMANO SATOSHI , KIMURA TETSUYA
IPC分类号： H05K3/20 , H01L23/12 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To prevent oxidation of a surface of a metal foil when a circuit pattern is formed by using the metal foil and reduce contact resistance with viahole conductor. SOLUTION: The metal foil wherein an oxidation preventing film 15 constituted of a metal layer whose thickness is 0.003 to 1 μm and main component is anyone out of Ag, Ni, Zn, Sn, Cr, Pb and Al is formed on at least a surface side which is in contact with air is stuck on a surface of prescribed transfer material 14 and worked to prescribed circuit patterns, and wiring circuit layers 17a, 17b are formed. After the oxidation preventing films 15 on surfaces of the wiring circuit layers 17a, 17b are eliminated, the circuit patterns are transferred to green sheets 11 containing prescribed ceramic component. The green sheets 11a, 11b on which the circuit patterns are transferred are laminated and baked. COPYRIGHT: (C)2003,JPO

47. 发明专利

JP2003152337A METHOD OF MANUFACTURING MULTILAYER WIRING BOARD 审中-公开
公开(公告)号：JP2003152337A
公开(公告)日：2003-05-23
申请号：JP2001352823
申请日：2001-11-19
申请人： KYOCERA CORP
发明人： HAMANO SATOSHI , SHIGEOKA TOSHIAKI , KIMURA TETSUYA , TAMI YASUHIDE
IPC分类号： C04B35/64 , H01L23/12 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer wiring board whose surface layer can be prevented from varying in thickness even after a constraining sheet is removed. SOLUTION: A constraining green sheet 3 contains ceramic powder, and the same coloring agent is contained in both a glass ceramic green sheet 1 and the constraining green sheet 3.

48. 发明专利

JP2002050869A METHOD OF MANUFACTURING MULTILAYERED WIRING BOARD 失效
公开(公告)号：JP2002050869A
公开(公告)日：2002-02-15
申请号：JP2000230913
申请日：2000-07-31
申请人： KYOCERA CORP
发明人： KIMURA TETSUYA , TAMI YASUHIDE
IPC分类号： H05K3/46 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing multilayered wiring board by which a multilayered wiring board can be manufactured with high dimensional accuracy by reducing the width and resistance of wiring. SOLUTION: In the method, the multilayered wiring board A having wiring circuit layers 3 formed on and/or in a glass-ceramic wiring board 10 is manufactured in such a way that green sheets 1 each of which contains glass powder and ceramic powder and carries a wiring circuit layer 3 on its surface are laminated upon another and a restricting sheet 8 composed mainly of a hard-to- sinter ceramic material and containing an amorphous component of 0.5-15 vol.% is laminated upon at least one surface of the laminated body of the green sheets 1. Then the laminated body is baked at a temperature lower than the melting point of the wiring circuit layers 3. The average difference between the coefficients of thermal expansion of the substrate 10 and restricting sheet 8 at 40-400 deg.C is adjusted to

49. 发明专利

JP2001102756A MULTILAYER WIRING BOARD AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2001102756A
公开(公告)日：2001-04-13
申请号：JP27505599
申请日：1999-09-28
申请人： KYOCERA CORP
发明人： KIMURA TETSUYA , ONIZUKA KATSUHIKO
IPC分类号： H05K1/11 , H05K1/03 , H05K1/09 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board which attains a fine wiring structure and the dimension stability of a glass ceramic wiring board, can be stably manufactured by simultaneously baking metal foils and glass ceramic moldings, and has superior mounting reliability also for external circuit boards such as printed wiring boards. SOLUTION: This wiring board comprises a glass ceramic insulation board 2 and wiring circuit layers 3 formed in the insulation board 2. The insulation board comprises, at least in the interior, inner wiring layers composed of high- purity metal conductors having a metal content of 99.5 wt.% or more which are composed of foils, of at least one metal selected from among Cu, Ag, Al, Au, Ni, Pt and Pd. The insulation board 1 is made of glass ceramics, having a Young's modulus of 120 GPa or less.

50. 发明专利

JP2000349200A WIRING BOARD 失效
公开(公告)号：JP2000349200A
公开(公告)日：2000-12-15
申请号：JP2000115683
申请日：2000-04-17
申请人： KYOCERA CORP
发明人： TERASHI YOSHITAKE , KAWAI SHINYA , KIMURA TETSUYA , KUMADAWARA HITOSHI , TAMI YASUHIDE
IPC分类号： C04B35/195 , H01L23/12 , H01L23/15 , H05K1/03 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a wiring board which is burned at a temperature of 800 to 1000 deg.C, low in dielectric constant and low in dielectric loss in a high-frequency region, high in mechanical strength, similar to a printed board in thermal expansion coefficient, and high in mounting reliability. SOLUTION: A mixture of 50 to 95 wt.% glass powder which is capable of separating out diopside oxide crystal phase (DI) which contains SiO2, Al2O3, MgO and CaO, and 5 to 50 wt.% in a total weight of quartz powder and/or amorphous silica powder is molded and burned into a porcelain board which contains diopside oxide crystal phase (DI) and SiO2 crystal phase (Si), has a thermal expansion coefficient of 8.5 ppm/ deg.C or above in a temperature range from a room temperature to 400 deg.C, and is made to serve as the insulating board for a wiring board.

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