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    • 43. 发明专利
    • ABSOLUTE POSITION DETECTING METHOD USING DOUBLE-SPEED RESOLVER
    • JPH01119717A
    • 1989-05-11
    • JP27742687
    • 1987-11-04
    • HITACHI LTD
    • SAKAI KEIJIROMUTO NOBUYOSHITOMITA HIROYUKICHIBA HIROSHIUEDA AKITERU
    • G05D3/12G01B7/00G01B7/30G01D5/245
    • PURPOSE:To detect the absolute position from the mechanical origin with high accu racy, by judging the absolute position of the position detection value of a plural (P) pole logarithmic resolver on the basis of the detection value of a single pole logarith mic resolver. CONSTITUTION:A double-speed resolver 4 is directly connected to an induction machine 1 and constituted of a single pole logarithmic resolver 2 and a P-pole resolver 3. The two-phase exciting signal of the resolver 4 is outputted as an exciting phase theta0 through an exciting circuit 7 by counting the reference clock signal fc of an one-chip microcomputer 5. On the basis of rotary position detection values theta1x, thetapx obtained by latching the phase theta0 on the basis of the zero phases of the output signals of the respective resolvers 2, 3 by latches 91x, 9px and respectively changing within a ranges of 360 deg. and (360/P) deg., the rotary position of the rotor of an electromotor is detected. At this time, on the basis of the dividing number N obtained by dividing the detection value theta1x of the resolver 2 at every arbitrary range and the detection value thetapx of the resolver 3, the absolute position of the rotor is detected. As mentioned above, a position is detected from the detection value thetapx fundamentally but an absolute value is judged from the detection value theta1x.
    • 49. 发明专利
    • DETECTING METHOD FOR FAULT OF SPEED DETECTOR
    • JPS61189460A
    • 1986-08-23
    • JP2829085
    • 1985-02-18
    • HITACHI LTD
    • MUTO NOBUYOSHISAKAI KEIJIROUEDA AKITERUNINOMIYA JUICHI
    • G01P3/42G01P3/44
    • PURPOSE:To detect a phase lack rapidly even if a speed change range is wide by detecting respective levels of a speed signal of another phase and a inverted speed signal on the basis of the leading edge and trailing edge of the inverted speed signal. CONSTITUTION:When the phase of a speed signal (a) is lacked, a latch 110 enters the 'L' level of the signal (a) at the leading edge of a speed signal (b) and outputs an 'L' output (c). On the other hand, an inverted speed signal a' inputted at the leading edge of an inverted speed signal b' is turned to 'H' and the output (d) of a latch 111 is always fixed. Signals (f) and (g) are the same as the normal state. Consequently, the dissidence of only the levels of both the signals (c), (d) is detected by an EXOR circuit 12A. When the level of the output (e) of the circuit 12A is turned to 'H', a differential pulse (i) is generated 13 and a CPU11B is interrupted to detect the lack of the phase. On the other hand, the pulse (i) is latched 14 and the CPU11B decides the phase lack of the signal (a) and executes the fault detecting processing of a rotary encoder 53.