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41. 发明专利

JPS6467674A MICROPROCESSOR SYSTEM 失效
公开(公告)号：JPS6467674A
公开(公告)日：1989-03-14
申请号：JP22395887
申请日：1987-09-09
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HASHIMOTO KOJI , HASEGAWA ATSUSHI , KAWASAKI IKUYA , IWASAKI KAZUHIKO
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To prevent data transferring efficiency from being lowered by supplying information, which show a data storing position to be a data transferring source or a data transferring destination, to a co-processor, causing the co- processor to be independent together with a main processor and supervising the number of a series of data transferrings or the end of a series of data transferring operation. CONSTITUTION:A main processor 1 stores the number of data transferring to be needed for access control to the data transferring. For a co-processor 2, since a resistor to be supplied for the data transferring is designated by a command and a parameter supplied from the main processor 1, the exchange of information besides it is not needed and the data transferring operation is executed. Thus, the decreasing of an over-head between the main processor 1 and the co-processor 2 in such data transferring operation can be achieved.

42. 发明专利

JPS6435647A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS6435647A
公开(公告)日：1989-02-06
申请号：JP19008087
申请日：1987-07-31
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI ENG CO LTD
发明人： IWASAKI KAZUHIKO , KAWASAKI IKUYA , FUNABASHI TSUNEO , INAYOSHI HIDEO , HASEGAWA ATSUSHI , YAGINUMA TAKAO , KONDO EIKI
IPC分类号： G06F9/38 , G06F15/16
摘要： PURPOSE:To enable transfer between a memory and a CP through one bus cycle by adding a coprocessor space signal (CPS) and a coprocessor cycle signal (CPCYCL) or a command transfer cycle signal (AT2-0) to a coprocessor in addition to an ordinary memory access signal of a microprocessor. CONSTITUTION:When the microprocessor MPU1 fetches an instruction, which a coprocessor CP should process, it transmits an instruction CPS corresponding to this to the CP. At such a time, it transmits the AT2-0, showing that is is the bus cycle to transfer the instruction to the CP as well to the CP together with the instruction. In case of an operand is transferred from the memory 3 to the CP, the MPU1 asserts the signal CPYCL, showing the effectiveness of CP data in addition to the signal of ordinary memory read, and instructs the CP to fetch the data, and performs the transfer between the memory and the CP. In case of the data is transferred from the CP to the memory, the MPU asserts the CPCYCL signal, and instructs the CP to output the data to perform the transfer.

43. 发明专利

JPS63155336A DATA PROCESSOR 失效
公开(公告)号：JPS63155336A
公开(公告)日：1988-06-28
申请号：JP30130686
申请日：1986-12-19
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NARITA SUSUMU , HASEGAWA ATSUSHI , MASUDA SATOSHI
IPC分类号： G06F11/28 , G06F11/36 , G06F15/78
摘要： PURPOSE:To facilitate the debug of software by supplying a single comparison result, a combination of plural comparison results, a single comparison result and its history or a combination of plural comparison results and its histories to a break control circuit. CONSTITUTION:When the break subject is equal to an address, an address ADR showing a break point is set on a comparison register CMP in a chip. When an access occurs, the address to receive an access is compared with the value set on the register and the result of this comparison is supplied to a break control circuit BRCNT. The circuit BRCNT monitors the result of comparison and using combination of the monitor results and the history of the comparison result as inputs to decide whether the designated conditions are satisfied or not, that is, a break is produced or not. Thus the complicated break conditions can be designated.

44. 发明专利

JPS6383851A SYSTEM FOR DISCRIMINATING INPUT/OUTPUT DATA 失效
公开(公告)号：JPS6383851A
公开(公告)日：1988-04-14
申请号：JP22818586
申请日：1986-09-29
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： IWASAKI KAZUHIKO , AOKI HIROKAZU , KAWASAKI IKUYA , HASEGAWA ATSUSHI , FUNABASHI TSUNEO
IPC分类号： G06F13/42 , G06F15/78
摘要： PURPOSE:To omit the external circuits and to increase the data access speed by using plural input pins for data complete signals and producing an OR within a microprocessor. CONSTITUTION:The inverse of DC0 input signal is supplied to test machine 21 via an inverter 28, a NOR gate 29 and an inverter 30, while the inverse of DC1 input signal is supplied to the machine 21 via an inverter 32, the gate 29 and the inverter 30 respectively. For the input signal of a microprocessor, plural inverters are generally cascaded at the stages following an input pad. These inverters are replaced with NOR and an OR is secured. The circuit delay due to the cascade of inverters and the circuit delay caused when the circuit delay serves as a NOR by an amount equal to a stage are very small in a CMOS process. Thus it is not required to produce an OR through an external circuit, therefore, the data access speed is increased.

45. 发明专利

JPS6379162A CONTROL SYSTEM FOR TRANSFERRING PROCESSOR DATA 失效
公开(公告)号：JPS6379162A
公开(公告)日：1988-04-09
申请号：JP22358786
申请日：1986-09-24
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： HASHIMOTO KOJI , HASEGAWA ATSUSHI , KAWASAKI IKUYA , IWASAKI KAZUHIKO
IPC分类号： G06F15/16 , G06F9/312 , G06F9/38 , G06F15/177
摘要： PURPOSE:To decrease the overheads between a main processor and a coprocessor during transfer of data by storing the data transfer frequency, etc., needed for access control through the main processor for transfer of data. CONSTITUTION:For instance, an instruction set supplied from outside indicates transfer of data between a memory M and a large-number register BR of a coprocessor CMPU. Thus a main processor MMPU transfers a command for execution of transfer of data and an operand for designation of each necessary register to the CMPU. While the MMPU decodes the instruction set for transfer of data to store the data transfer frequency to the BR and the address of the memory M needed for transfer of data. Then the MMPU performs the access control of the M synchronously with the working of the CMPU. Thus data are transferred to the BR of the CMPU from the M and data of the BR are written to the M.

46. 发明专利

JPS6355638A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS6355638A
公开(公告)日：1988-03-10
申请号：JP19886886
申请日：1986-08-27
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , SAKAMURA TAKESHI
发明人： SAKAMURA TAKESHI , KAWASAKI IKUYA , HASEGAWA ATSUSHI , KUBO MITSUYUKI , IWASAKI KAZUHIKO
IPC分类号： G06F12/02 , G06F9/34 , G06F9/35 , G06F12/06
摘要： PURPOSE:To improve the diversion properties of the software set between a lower device type and a higher device type by providing a bit to an operand designator contained in an instruction word to designate the size of an address space and therefore indreasing the no load of hardware. CONSTITUTION:An operand designator EA consists of an addressing mode designating part AM, a size designating bit P for address pointer, and an additional part AD. The pointer P includes all registers indicating addresses. Therefore the pointer P contains a program counter, a stack pointer and frame pointer which is used for delivery of a parameter for subroutine call.

47. 发明专利

JPS6355634A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS6355634A
公开(公告)日：1988-03-10
申请号：JP19887086
申请日：1986-08-27
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , SAKAMURA TAKESHI
发明人： SAKAMURA TAKESHI , NAKAZAWA TAKUICHIROU , HASEGAWA ATSUSHI , KAWASAKI IKUYA , IWASAKI KAZUHIKO
IPC分类号： G06F9/305 , G06F7/00 , G06F9/308 , G06F9/34 , G06F12/04
摘要： PURPOSE:To shorten the instruction executing time by omitting the calculation carried out for decision of the boundary cross when a limited bit field instruction is executed and obtaining the offset value and the field width as the immediate values. CONSTITUTION:An LSI chip 1 forming a microprocessor contains a micro ROM 2 storing a microprogram. While the signal obtained by decoding the code of a microinstruction fetched by an instruction register 3 by an instruction decider 4 is supplied to a microaddress generating circuit 5. The circuit 5 produces the corresponding microaddress based on said received signal and supplied the microaddress to the ROM 2. The microinstruction has such an instruction style that has a designating part that applies the offset value and the field value as the immediate values independently of a bit field instruction.

48. 发明专利

JPS61136145A Cache memory control circuit 失效
标题翻译：缓存记忆控制电路
公开(公告)号：JPS61136145A
公开(公告)日：1986-06-24
申请号：JP25758984
申请日：1984-12-07
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： HASEGAWA ATSUSHI , KAWASAKI IKUYA , NISHIMUKAI TADAHIKO
IPC分类号： G06F12/08
摘要： PURPOSE: To decrease the overheads in a mishit mode by starting immediately an access of a main memory before the retrieval result of a cache memory is obtained in the next data access mode if no hit is given to the cache memory in the preceding data access mode.
CONSTITUTION: In case a cache memory has no hit in the preceding read mode, i.e., '0' is stored to a flip-flop 7, a processor 1 delivers an address to be read out to an address signal 100 and turns on a start signal 102. Then a signal 107 is turned on since the flip-flop 7 holds '0'. thus a memory read signal 111 is immediately turned on by an AND gate 8 to give a read indication to a memory device 11. While the cache memory is retrieved and read out in the same way as a hit mode.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：如果在先前的数据访问模式下没有对高速缓冲存储器进行命中，则在下一个数据访问模式下获得高速缓冲存储器的检索结果之前，通过立即启动主存储器的访问来减少虚拟模式的开销。构成：如果高速缓冲存储器在前一读取模式下没有命中，即，“0”被存储到触发器7，则处理器1将要读出的地址传送到地址信号100并且开始然后信号107导通，因为触发器7保持“0”。因此存储器读取信号111被AND门8立即接通，以向存储器件11提供读取指示。虽然以与命中模式相同的方式检索和读出高速缓冲存储器。

49. 发明专利

JPS6159554A Cache memory control circuit 失效
标题翻译：缓存记忆控制电路
公开(公告)号：JPS6159554A
公开(公告)日：1986-03-27
申请号：JP18043484
申请日：1984-08-31
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： UCHIYAMA KUNIO , HASEGAWA ATSUSHI , AIMOTO TAKESHI , NISHIMUKAI TADAHIKO
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： PURPOSE: To enhance a hit rate of a cache memory and obtain a small capacity and efficient cache memory by assigning the specified area for data of high iterative availability ratio.
CONSTITUTION: When a storage device stores in a stack access mode, it writes data on a signal 121 in an address, which a signal 119 shows. At the same time, retrieval of an associative memory 26 is executed, and the result is outputted to a signal 118. At the completion of data writing, the storage device turn on a signal 115 and the write is designated again to the associative memory 26. When an address coincident with a write address is absent in the memory 26, an address and data is written in an entry shown by a counter 24 at OFF of a signal 118. When an address coincident with the write address is present, only data is written in the entry of the memory 26 at ON of the signal 118. Thus, in case of storing in the stack access mode, data stored in the storage device is always written into the memory 26.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过为具有高迭代可用率的数据分配指定的区域来提高高速缓存的命中率，并获得小容量和高效的缓存。构成：当存储设备以堆栈访问模式存储时，它将数据写入地址中的信号121，信号119显示。同时，执行关联存储器26的检索，并将结果输出到信号118.在完成数据写入时，存储装置打开信号115，并将写入再次指定给关联存储器26 当在存储器26中不存在与写入地址一致的地址时，地址和数据被写入由信号118的OFF处的计数器24所示的条目中。当存在与写入地址一致的地址时，仅存在数据在存储器26的入口处写入信号118的ON。因此，在存储在堆栈访问模式的情况下，存储在存储设备中的数据总是被写入存储器26。

50. 发明专利

JPS60256855A CACHE MEMORY CONTROL CIRCUIT 失效
公开(公告)号：JPS60256855A
公开(公告)日：1985-12-18
申请号：JP11076484
申请日：1984-06-01
申请人： HITACHI LTD , HITACHI MAIKURO ENGINEERING KK
发明人： NISHIMUKAI TADAHIKO , HASEGAWA ATSUSHI , MATSUMURA MASARU
IPC分类号： G06F12/08
摘要： PURPOSE:To attain data processing with no conflict by holding the data on access to a specific area at a cache memory in case a processor gives access to a memory means having varying memory contents. CONSTITUTION:For an instruction control circuit 10, a read signal 114 is turned on by an inverter 28 and an AND gate 29 to indicate reading to an external memory when a signal 112 turns on since a signal 119 is kept off in case an associative memory 20 stores no read data. At the same time, a comparator 19 compares an address signal 116 with the values of registers 16 and 17. A signal 115 is turned off in case an address is set between the lower and upper limit values held in a register. The external memory outputs the read data to a signal 121 when the reading action is over and turns on an end signal ACK113. Thus a signal 110 is turned on via an OR gate 23. Then the circuit 10 writes the data read out to a register 14 to complete its operation.

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