专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

JPH11122064A PEAK VALUE DETECTING CIRCUIT AND BURST SIGNAL AMPLIFIER 失效
公开(公告)号：JPH11122064A
公开(公告)日：1999-04-30
申请号：JP28514997
申请日：1997-10-17
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKAHASHI YASUSHI , YUMOTO OSAMU , NAKAMURA MAKOTO , ISHIHARA NOBORU , AKAZAWA YUKIO
IPC分类号： H03G3/20 , H03D1/18 , H03K5/02 , H04B10/07 , H04B10/29 , H04B10/40 , H04B10/50 , H04B10/60 , H04B10/69 , H04L25/03 , H04B10/04 , H04B10/06 , H04B10/14 , H04B10/26 , H04B10/28
摘要： PROBLEM TO BE SOLVED: To increase charging speed and to make detected voltage hold time long through the decrease in peak value storage capacity by adding a circuit which prevents electric charges from flowing out of the peak value storage capacity. SOLUTION: An input burst signal is inputted to the base of a 1st transistor 13 as an emitter follower via a two-input amplifier 11. The peak value storage capacity 12 connected between the emitter and ground is charged to a value which is proportional to the peak value of the input signal. Its voltage is outputted from an output terminal 21 via a buffer consisting of 2nd, 3rd, and 4th Darlington-connected transistors 14, 15, and 16 of the trailing stage. At the same time, this output voltage is supplied as a reference voltage to the other input terminal of the two-input amplifier 11. A base current Ib2 of the 2nd transistor 14 becomes smaller by just 1/(hfe2×hfe4) than the collector current Ic4 of the 4th transistor 16, so that the hold time of electric charges of the peak value storage capacity 12 becomes long.

42. 发明专利

JPH09246880A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH09246880A
公开(公告)日：1997-09-19
申请号：JP7534596
申请日：1996-03-05
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAMURA MAKOTO
IPC分类号： H01L31/10 , H03F3/08 , H04B10/40 , H04B10/50 , H04B10/60 , H04B10/69 , H04B10/04 , H04B10/06 , H04B10/14 , H04B10/26 , H04B10/28
摘要： PROBLEM TO BE SOLVED: To obtain a preamplifier circuit for light reception with a stably high sensitivity and a broad band circuit by providing a common source amplifier circuit, a source follower circuit and an impedance element or the like. SOLUTION: A common source circuit is configured by a common source amplifier transistor(TR) 2 and an active load 3, a parallel feedback amplifier circuit is configured by the common source circuit, a source follower TR 4 of an output buffer and a feedback resistor 7, and the active load 3 is made up of a FET. Then an input terminal 1 of an amplifier circuit AMP 1 and a gate of the active load 3 are connected by a phase compensation capacitor 8 to compensate a high frequency component of an input signal and to obtain a broad band characteristic. Furthermore, a phase of a high frequency signal to be compensated is changed by connecting an impedance 9 in series with the capacitor 8 to compensate the phase of the amplifier AMP1. Since the phase lag at a high frequency in a negative feedback amplifier circuit is compensated, the amplifier operation is made stable.

43. 发明专利

JPH0746092A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH0746092A
公开(公告)日：1995-02-14
申请号：JP20853893
申请日：1993-07-30
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAMURA MAKOTO , ISHIHARA NOBORU , AKAZAWA YUKIO
IPC分类号： H03K5/02 , H03K5/08
摘要： PURPOSE:To fix output data at a low level by shifting the threshold value of an amplifier against reception data in a non-signal period after a reset signal is generated until a burst signal is inputted in an amplifier circuit for amplifying the burst signal. CONSTITUTION:The threshold value of the amplifier 11 in the non-signal period after the reset signal is generated until the burst signal is received is made lower than the value of the reception data and the output data of this amplifier circuit 10 in the non-signal period is turned to a low value. In such a manner, a state for causing code errors between the burst signal and the next burst signal is eliminated. In the meantime, the intermediate voltage of the output voltage of a top holding circuit T for holding the maximum value of the reception data and the fixed voltage of a fixed voltage source 13 is applied to an output terminal 112 corresponding to resistance division by resistors R11 and R12, the circuit T follows the maximum value of the burst signal after the burst signal is received and the threshold value to be supplied to the threshold value terminal 112 of the amplifier 11 is turned to the value close to an optimum.

44. 发明专利

JPH05327405A VOLTAGE CONTROLLED PHASE SHIFTER 失效
公开(公告)号：JPH05327405A
公开(公告)日：1993-12-10
申请号：JP14679792
申请日：1992-05-14
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAMURA MAKOTO , IMAI YUUKI , SANO EIICHI , KIMURA SHUNJI
IPC分类号： H03H11/20
摘要： PURPOSE:To reduce an output amplitude fluctuation where of an output is changed. CONSTITUTION:A 3rd signal with a different phase from 1st and 2nd input signals VI1, VI2 and an equal amplitude to them is generated by a fixed phase shifter 23, and the voltage controlled phase shifter is featured to have a 1st variable phase shifter 21 receiving the 1st input signal VI1 and the 3rd signal and a 2nd variable phase shifter 22 receiving the 2nd input signal VI2 and the 3rd signal, and an output of both the variable phase shifters 21, 22 is selected by a channel changeover circuit 24 to obtain an output whose phase is varied with less amplitude fluctuation.

45. 发明专利

JPH05315851A BROAD BAND DC AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH05315851A
公开(公告)日：1993-11-26
申请号：JP14109492
申请日：1992-05-07
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： IMAI YUUKI , NAKAMURA MAKOTO , KIMURA SHUNJI
IPC分类号： H03F1/42 , H03F3/60 , H03H11/04
摘要： PURPOSE:To obtain a DC amplifier circuit operated for a wide band by forming a constant K filter circuit with a capacitor of a transistor(TR) and an inductor or a transmission line and connecting the circuit in multi-stage to form a distributed line. CONSTITUTION:A unit circuit employs a unit amplifier stage 9 and a unit DC level shift stage 10, and a capacitance between an input terminal 5 of each of the unit circuits 9, 10 and an electric ground is used for a parallel element. Moreover, an output side constant K filter circuit is formed by using a capacitance between an output terminal 6 of each of the unit circuits 9, 10 and ground for a parallel element and using an inductor 11 connecting in series with an output terminal 6 for a series element. The constant K filter circuit is connected in multi-stage to form input and output distributed lines 200, 300 for an amplifier stage 9 and a DC level shift stage 10. Through the constitution above, the effect of the frequency characteristic of the capacitance of the TR 1 is compensated and the broad band operation is attained.

46. 发明专利

JPH05315845A FREQUENCY CONVERSION CIRCUIT 失效
公开(公告)号：JPH05315845A
公开(公告)日：1993-11-26
申请号：JP14109692
申请日：1992-05-07
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： IMAI YUUKI , NAKAMURA MAKOTO , KIMURA SHUNJI
IPC分类号： H03D7/12 , H03D9/06
摘要： PURPOSE:To attain a low spurious operation over a wide band by forming a matching circuit for a high frequency terminal and a local oscillation terminal with a distributed line comprising the repetition of a constant K filter circuit comprising a capacitance of a transistor(TR) and an inductance. CONSTITUTION:A distributed amplifier circuit is formed in the frequency conversion circuit by connecting a unit circuit employing a source earth or an emitter earth FET21 in multi-stages. An input terminal of the distributed amplifier circuit is used for a high frequency terminal RF13 and one terminal of an output side is used for a local oscillation terminal LO14, and the other terminal at the output side corresponding to the output terminal of the distributed amplifier circuit is used for an intermediate frequency terminal IF15. Through the constitution above, the high frequency terminal RF13 and the local oscillation terminal LO14 are formed by the distributed amplifier circuit being multi-stage processing of the constant K filter circuits. Since the capacitor of the FET21 is used for a component of the distributed line, deterioration in the capacitor is compensated and a broad band mixer operation is attained and a low spurious operation is realized.

47. 发明专利

JPH04306908A LIMITER AMPLIFIER 失效
公开(公告)号：JPH04306908A
公开(公告)日：1992-10-29
申请号：JP7107291
申请日：1991-04-03
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： IMAI YUUKI , NAKAMURA MAKOTO
IPC分类号： H03F3/19 , H03G11/00
摘要： PURPOSE:To attain low phase deviation even at a high frequency by connecting an input and an output of a circuit including a phase shifter respectively to an input terminal and an output terminal of the amplifier having a limiter characteristic. CONSTITUTION:An input terminal and an output terminal of a signal line of a circuit including a phase shifter 12 such as a circuit comprising the phase shifter 12 and an attenuator 13 are respectively connected to an input terminal and an output terminal of an amplifier 10 having a limiter characteristic. Then an output of the limiter amplifier 10 whose phase changes with an input increase and an output of a circuit comprising the phase shifter 12 whose phase is constant but whose amplitude changes with an input increase are synthesized. Thus, a phase deviation in the output of the limiter amplifier 10 is reduced at a proper phase of the phase shifter 12.

48. 发明专利

JPH03241952A VOICE SWITCH 失效
公开(公告)号：JPH03241952A
公开(公告)日：1991-10-29
申请号：JP3805890
申请日：1990-02-19
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： OIKAWA HIROSHI , FUKUYO YOSHIHIRO , HIDAKA KENJI , NAKAMURA MAKOTO
IPC分类号： H04R3/02 , H04B3/20 , H04M1/60
摘要： PURPOSE:To keep the position of a participant/trainee in the transmission state by inhibiting the changeover state into a reception state when a reception signal comes during the talking state and a predetermined time does not elapse. CONSTITUTION:Even when a condition of switching the transmission state into the reception state takes place depending on the relation of a reception signal level and a transmission signal level, a counter CTA to inhibit the changeover and a counter CT realizing hangover time till the setting time by a delay time setting switch 30 elapses are realized by the software by a CPU 10a and a ROM 10c. Thus, even when the condition causing the reception state tentatively for its own echo takes place, the stable state is awaited and the talking state is kept and continued during the transmission or during a pause in the transmission state.

49. 发明专利

JP2003149613A OPTICAL MODULATION CIRCUIT 审中-公开
公开(公告)号：JP2003149613A
公开(公告)日：2003-05-21
申请号：JP2001345640
申请日：2001-11-12
申请人： NIPPON TELEGRAPH & TELEPHONE , NTT ELECTRONICS CORP
发明人： KANDA ATSUSHI , NAKAMURA MAKOTO
IPC分类号： G02F1/015 , H01L33/12 , H01S5/062 , H03K5/04 , H03K17/78 , H01L33/00
摘要： PROBLEM TO BE SOLVED: To realize an optical modulation circuit capable of high quality signal transmission by compensating and reducing the influence of nonlinearity of an optical element being an external load of the optical modulation circuit and the influence of a nonlinear noise such as distortion that occurs in an optical modulation system. SOLUTION: This optical modulation circuit is provided with a duty rate adjustment circuit capable of adjusting the duty rate of an output signal, and is constituted so that it adjusts the duty rate by measuring a monitor of signal waveform modulated by the optical element or an error rate of a transmission signal, and feeding back the measured results to the duty rate adjustment circuit so as to be in the best state. Also, it is constituted so that the duty rate of the signal waveform is adjusted by inputting a single-phase signal to one input of a differential amplifier constituting an inputting part of the duty rate adjustment circuit for duty rate adjustment, applying the fed back signal to the other input, and supplying an output of the differential amplifier to a limiter amplifier.

50. 发明专利

JPH08213979A TIMING EXTRACTING CIRCUIT 失效
公开(公告)号：JPH08213979A
公开(公告)日：1996-08-20
申请号：JP4243095
申请日：1995-02-07
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAMURA MAKOTO , ISHIHARA NOBORU
IPC分类号： H03L7/00 , H04L7/033
摘要： PURPOSE: To momently extract the phase or a clock signal against a burst input data signal by taking the invertion signal of exclusive OR between an input data signal and data, which is obtained by delaying the input data signal by a specific period phase of the transmission rate, as a gating signal. CONSTITUTION: A delay circuit 11 which delays the input data signal by a 1/2 period phase of the transmission rate and an exclusive OR circuit 12 which takes exclusive OR between the signal delayed in this manner by the delay circuit 11 and the input data signal are provided. A logic inverting circuit 13 which inverts the output signal of the exclusive OR circuit 12 to output the gating signal and a voltage controlled oscillator 20 which controls oscillation by the gating signal are provided. Thus, the clock signal can be continuously sent even at the time of continuity of the same code. Consequently, the phase of the clock signal is momently extracted against burst input.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式