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41. 发明专利

JP2007012848A Semiconductor memory device and its manufacturing method 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2007012848A
公开(公告)日：2007-01-18
申请号：JP2005191257
申请日：2005-06-30
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： ISHINO MASAKAZU , IKEDA HIROAKI , SHIBATA KAYOKO
IPC分类号： H01L25/065 , H01L21/8242 , H01L25/07 , H01L25/18 , H01L27/108
CPC分类号： H01L21/6835 , G11C5/02 , G11C5/025 , H01L23/481 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/81005 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/06596 , H01L2924/00014 , H01L2924/15311 , H01L2924/1532 , H01L2924/15787 , H01L2924/181 , H01L2924/30105 , H01L2224/81 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To restrain reduction of reliability and facilitate specification changes of a semiconductor memory device configured by a plurality of core chips and interface chips. SOLUTION: This semiconductor memory device comprises an interposer chip 110 where a first inner electrode 141 connected to core chips 131 to 134 is formed on a first face 110a. A second inner electrode 142 for connecting to an interface chip and a third inner electrode 143 for connecting to an external terminal are formed on a second face 110b. Since the interface chips can be post-mounted to the second face 110b side of the interposer chip 110, products of different specifications can be produced simply and separately. That is, since appropriate interface chip may be post-mounted, in response to user's demands, it is not necessary to have a large quantity of core chips in a bare-chip state stocked. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了抑制由多个核心芯片和接口芯片构成的半导体存储器件的可靠性的降低和便于规范变化。解决方案：该半导体存储器件包括插入器芯片110，其中连接到芯片芯片131至134的第一内部电极141形成在第一面110a上。用于连接到接口芯片的第二内部电极142和用于连接到外部端子的第三内部电极143形成在第二面110b上。由于接口芯片可以被后置安装到插入器芯片110的第二面110b侧，所以可以简单且分开地生产不同规格的产品。也就是说，由于适当的接口芯片可以被后置安装，响应于用户的要求，不需要在裸芯片状态下存储大量的芯片芯片。版权所有（C）2007，JPO＆INPIT

42. 发明专利

JP2006301863A Memory module 有权
标题翻译：记忆模块
公开(公告)号：JP2006301863A
公开(公告)日：2006-11-02
申请号：JP2005121210
申请日：2005-04-19
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IKEDA HIROAKI , ISHINO MASAKAZU
IPC分类号： G06F12/06 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： G11C7/10 , G11C5/02 , G11C5/063 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/01055 , H01L2924/15192 , H01L2924/15311 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a memory module which can switch operations according to the model of a memory chip. SOLUTION: This memory module has memory core chips 10a-10d which have a relay wiring for electrically connecting an interface chip and an interposer chip and are placed between the interface chip and the interposer chip, the interposer chip 40 which sends out model information of the memory core chip to the interface chip through the relay wiring, and the interface chip 30 which controls the memory core chip in response to the model information received from the interposer chip. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供可以根据存储芯片的型号切换操作的存储器模块。解决方案：该存储器模块具有存储芯片10a-10d，其具有用于电连接接口芯片和插入器芯片的中继布线，并且放置在接口芯片和插入器芯片之间，插入器芯片40发送模型存储芯片芯片通过继电器布线到接口芯片的信息，以及响应于从插入器芯片接收到的模型信息来控制存储器芯片的接口芯片30。版权所有（C）2007，JPO＆INPIT

43. 发明专利

JP2006019328A Laminated semiconductor device 有权
标题翻译：层压半导体器件
公开(公告)号：JP2006019328A
公开(公告)日：2006-01-19
申请号：JP2004192763
申请日：2004-06-30
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： FUKAISHI MUNEO , SAITO HIDEAKI , HAGIWARA YASUHIKO , MIZUNO MASAYUKI , IKEDA HIROAKI , SHIBATA KAYOKO
IPC分类号： H01L25/18 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L25/065 , H01L25/07 , H01L27/00 , H01L27/04
CPC分类号： H01L23/525 , G11C5/02 , G11C5/04 , H01L23/481 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01019 , H01L2924/13091 , H01L2924/3011 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent the reduction of yield due to defective penetrated wiring in a laminated semiconductor device that is formed by stacking a plurality of semiconductor chips and uses wiring penetrating through the semiconductor chips to establish electric connection among the semiconductor chips. SOLUTION: The laminated semiconductor device includes penetrated wirings 205 and 209 penetrating through semiconductor chips 204 and 213. In this case, spare penetrated wirings 206 and 210 are arranged parallel to the penetrated wirings 205 and 209, and switch circuits 203, 207 and 211 are used to change over the transmittance route of a signal to the penetrated wiring or the spare penetrated wiring. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了防止由叠层多个半导体芯片形成的叠层半导体器件中的穿透布线不良引起的产量降低，并且使用贯穿半导体芯片的布线来建立半导体芯片之间的电连接。解决方案：层叠半导体器件包括穿透半导体芯片204和213的穿透的布线205和209.在这种情况下，备用的穿透布线206和210平行于穿透的布线205和209布置，并且开关电路203,207 和211用于将信号的透射路径改变为穿透的布线或备用的穿透布线。版权所有（C）2006，JPO＆NCIPI

44. 发明专利

JP2006012358A Stacked semiconductor memory device 有权
标题翻译：堆叠半导体存储器件
公开(公告)号：JP2006012358A
公开(公告)日：2006-01-12
申请号：JP2004191410
申请日：2004-06-29
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： SAITO HIDEAKI , HAGIWARA YASUHIKO , FUKAISHI MUNEO , MIZUNO MASAYUKI , IKEDA HIROAKI , SHIBATA KAYOKO
IPC分类号： G11C11/401 , G11C5/04 , G11C5/06 , G11C8/00 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/00 , H01L27/10
CPC分类号： G11C5/04 , G11C5/063 , H01L25/0657 , H01L2224/16145 , H01L2225/06527 , H01L2225/06555 , H01L2924/01019 , H01L2924/10253 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a three-dimensional semiconductor memory device capable of reducing a wiring capacity required for charge and discharge at the time of data transfer, thereby reducing power consumption. SOLUTION: The memory device comprises; a plurality of memory cell array chips which are stacked on a first semiconductor chip and have sub-banks resulting from dividing bank memories collectively arranged correspondingly to input and output bits; and inter-chip wires of which the number is equal to the number of the input and output bits and which connect the memory cell array chips in a form of piercing them in the stacking direction so that the sub-banks correspond to the same corresponding input and output bits. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供能够减少数据传送时的充放电所需的布线容量的三维半导体存储装置，从而降低功耗。解决方案：存储器件包括：多个存储单元阵列芯片，堆叠在第一半导体芯片上，并且具有由对应于输入和输出位共同排列的划分存储体而产生的子库; 芯片间线数等于输入和输出位的数量，并将存储单元阵列芯片以堆叠方向穿透的形式连接，使得子库对应于相同的相应输入和输出位。版权所有（C）2006，JPO＆NCIPI

45. 发明专利

JP2006012337A Stacked semiconductor memory device 有权
标题翻译：堆叠半导体存储器件
公开(公告)号：JP2006012337A
公开(公告)日：2006-01-12
申请号：JP2004190317
申请日：2004-06-28
申请人： Elpida Memory Inc , Nec Corp , エルピーダメモリ株式会社 , 日本電気株式会社
发明人： SAITO HIDEAKI , HAGIWARA YASUHIKO , FUKAISHI MUNEO , MIZUNO MASAYUKI , IKEDA HIROAKI , SHIBATA KAYOKO
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , H01L21/20 , H01L27/10 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： G11C5/025 , G11C5/02 , G11C5/063
摘要： PROBLEM TO BE SOLVED: To reduce development costs of many kinds of memory devices.
SOLUTION: This memory device has a memory cell array chip provided with a memory cell array, an interface chip which is stacked on the memory cell array chip and provided with a memory constitution switching circuit for changing an input and output bit constitution of the memory cell array, and a plurality of inter-chip wires for connecting the memory cell array chip and the interface chip.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决问题：降低多种存储器件的开发成本。解决方案：该存储器件具有设置有存储单元阵列的存储单元阵列芯片，接口芯片，其堆叠在存储单元阵列芯片上，并且具有用于改变输入和输出位构成的存储器结构切换电路存储单元阵列和用于连接存储单元阵列芯片和接口芯片的多个芯片间线。版权所有（C）2006，JPO＆NCIPI

46. 发明专利

JP2003044350A Register, memory module and memory system 有权
标题翻译：寄存器，存储器模块和存储器系统
公开(公告)号：JP2003044350A
公开(公告)日：2003-02-14
申请号：JP2001229230
申请日：2001-07-30
申请人： Eastern Japan Semiconductor Technologies Inc , Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社東日本セミコンダクタテクノロジ−ズ
发明人： NISHIO YOJI , SENBA SEIJI , SHIBATA KAYOKO , KANNO TOSHIO , IKEDA HIROAKI , IIZUKA TAKUO , TANMACHI MASAYUKI
IPC分类号： G11C11/407 , G06F12/00 , G06F12/06 , G11C7/10 , G11C8/00 , G11C8/06 , G11C11/409
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C2207/107
摘要： PROBLEM TO BE SOLVED: To provide a register capable of coping with a wide frequency range and without depending on the number of mounted devices. SOLUTION: First and second preprocessing flip-flop FF1a and FF1b latch a C/A signal (CAint) inputted in a register 40a with a clock (0.5WCLKint) having a frequency of a half of that of an external clock signal WCLK and its inversion clock. Thus, the C/A signal is temporarily extended to a set of signals (0.5CA-a and 0.5CA-b) having double cycle. Since the signals 0.5CA-a and 0.5CA-b have the double cycle of that of the C/A signal (CAint), first and second post-processing flip-flops FF2a and FF2b can perform the latch operations according to an internal clock signal intCLK generated by a DLL circuit in a state that the sufficient setup time and hold time are secured.
摘要翻译：要解决的问题：提供能够应付宽频率范围并且不依赖于安装的装置的数量的寄存器。解决方案：第一和第二预处理触发器FF1a和FF1b使用具有外部时钟信号WCLK的一半的频率的时钟（0.5WCLKint）来锁存在寄存器40a中输入的C / A信号（CAint），并且其反相时钟。因此，C / A信号被暂时扩展到具有双周期的一组信号（0.5CA-a和0.5CA-b）。由于信号0.5CA-a和0.5CA-b具有C / A信号（CAint）的双周期，因此第一和第二后处理触发器FF2a和FF2b可以根据内部时钟执行锁存操作在保证足够的建立时间和保持时间的状态下由DLL电路生成的信号intCLK。

47. 发明专利

JP2008187061A LAMINATED MEMORY 审中-公开
公开(公告)号：JP2008187061A
公开(公告)日：2008-08-14
申请号：JP2007020240
申请日：2007-01-31
申请人： ELPIDA MEMORY INC
发明人： IKEDA HIROAKI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To solve the problem that a laminated memory where a plurality of penetrating electrodes are required to individually access each layer because the penetrating electrodes are disposed at the same layout positions in the laminated memory and each layer is connected in parallel. SOLUTION: The laminated memory is such that a first memory chip and a second memory chip where the layout positions of ID penetrating electrodes for setting hierarchical recognition information of each layer are made different are alternately laminated. Internal circuits for the hierarchical recognition information of each layer are cascaded by alternately laminating them like this. The internal circuit can easily create the hierarchical recognition information of each layer. The laminated memory that can select an operation or non-operation of each layer is obtained by identifying these hierarchical recognition information. COPYRIGHT: (C)2008,JPO&INPIT

48. 发明专利

JP2006222252A SEMICONDUCTOR MEMORY AND LOAD-TEST METHOD THEREOF 审中-公开
公开(公告)号：JP2006222252A
公开(公告)日：2006-08-24
申请号：JP2005034009
申请日：2005-02-10
申请人： ELPIDA MEMORY INC
发明人： IKEDA HIROAKI , SHIBATA KAYOKO
IPC分类号： H01L25/18 , H01L21/3205 , H01L21/8242 , H01L23/52 , H01L25/065 , H01L25/07 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory wherein its core and its interface are so constituted respectively out of different chips from each other that its interface chip is not damaged, even though performing such a load test as a burn-in test. SOLUTION: The semiconductor memory has a core chip 110 having at least a formed memory cell, an interface chip 120 having at least a formed peripheral circuit to the memory cell, and an outside-terminal group. The outside-terminal group includes a power-supply terminal 131 for cores which is connected with the internal circuit of the core chip 110 and is not connected with the internal circuit of the interface chip 120, and includes a power-supply terminal 132 for interfaces which is connected with the internal circuit of the interface chip 120 and is not connected with the internal circuit of the core chip 110. Consequently, it is made possible that optimum operational voltages are given respectively to both the chips. COPYRIGHT: (C)2006,JPO&NCIPI

49. 发明专利

JP2003108512A DATA BUS WIRING METHOD, MEMORY SYSTEM AND MEMORY MODULE BASE BOARD 审中-公开
公开(公告)号：JP2003108512A
公开(公告)日：2003-04-11
申请号：JP2001297498
申请日：2001-09-27
申请人： ELPIDA MEMORY INC
发明人： ANPO HISASHI , IKEDA HIROAKI
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G11C5/00 , G11C5/06 , H01L27/10 , H05K1/02 , H05K1/14
摘要： PROBLEM TO BE SOLVED: To provide a data bus structure capable of eliminating unconformity of local impedance caused by additional capacity possessed by an integrated circuit such as a DRAM. SOLUTION: The impedance determined according to the additional capacity of a memory device is arranged in the vicinity of the memory device on a data bus.

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