专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

JP2004157574A Flatness simulation system for mask substrate 有权
公开(公告)号：JP2004157574A
公开(公告)日：2004-06-03
申请号：JP2004057990
申请日：2004-03-02
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MASAMITSU
IPC分类号： G03F1/84 , H01L21/027 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To realize a flatness simulation system for a mask substrate effective for solving the problem of lowering in the yield of products due to degradation in the flatness of the mask substrate by chucking the mask substrate to a mask stage of a water exposing device. SOLUTION: The flatness simulation system for mask substrate is characterized by being provided with a means for measuring the flatness of the substrate to acquire first information on the flatness of a major face of the mask substrate and a means for acquiring second information on the flatness of the major face by the simulation when the mask substrate is set at the exposing device from the first information and the information on the mask chuck structure of the exposing device. COPYRIGHT: (C)2004,JPO

42. 发明专利

JP2004046259A Inspection method of mask substrate, manufacturing method of exposure mask, and manufacturing method of semiconductor device 有权
标题翻译：掩模基板的检查方法，曝光掩模的制造方法和半导体器件的制造方法
公开(公告)号：JP2004046259A
公开(公告)日：2004-02-12
申请号：JP2003366387
申请日：2003-10-27
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MASAMITSU
IPC分类号： G03F1/60 , G03F1/84 , G03F7/20 , H01L21/027 , G03F1/08 , G03F1/14
摘要： PROBLEM TO BE SOLVED: To realize a mask substrate inspection method effective for solving a problem of production yield lowering due to deterioration in the flatness of the mask substrate which is caused by chucking the mask substrate on the mask stage of a wafer aligner. SOLUTION: A first piece of information is obtained that shows the mask substrate and the surface shape of its main surface (Step S1); a second piece of information is obtained that indicates the flatness of the main surface by simulation of setting the mask substrate in the aligner, from the flatness of the main surface of the mask substrate and the mask chuck structure of the aligner (Step S2); and judgement is made on whether or not the flatness of the main surface of the mask substrate as obtained by the simulation fits specifications (Step S3). COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了实现一种有效地解决由于将掩模基板夹在晶片对准器的掩模台上而导致的掩模基板的平坦度劣化的生产成品率降低问题的掩模基板检查方法。
解决方案：获得显示掩模基板及其主表面的表面形状的第一条信息（步骤S1）; 从掩模基板的主表面和对准器的掩模卡盘结构的平面度（步骤S2）获得指示主面的平坦度的第二信息，通过模拟设置对准器中的掩模基板的平面度。并判断通过仿真得到的掩模基板的主面的平坦度是否适合规格（步骤S3）。版权所有（C）2004，JPO

43. 发明专利

JP2017084871A テンプレート基板およびその製造方法有权
公开(公告)号：JP2017084871A
公开(公告)日：2017-05-18
申请号：JP2015208992
申请日：2015-10-23
申请人：株式会社東芝 , Toshiba Corp
发明人： KANEMITSU SHINGO , ITO MASAMITSU
IPC分类号： H01L21/027 , B29C59/02
CPC分类号： G03F9/7042 , G03F7/0002
摘要：【課題】アライメントマーク形成領域の光学的特性を充分に変化させ、高いアライメント精度を得ることができるテンプレート基板およびその製造方法を提供する。【解決手段】本実施形態によるテンプレート基板は、第1面と、第1面の反対側にある第2面とを備える。第1領域は、第1面上に設けられ周囲よりも突出している。第2領域は、第1領域の少なくとも端部にあり、パターンの転写時に用いられるアライメントマークが形成される予定の領域である。第2領域は、第1不純物と第2不純物とを含む。【選択図】図1

44. 发明专利

JP2011249567A Imprint mask, manufacturing method therefor, and semiconductor device manufacturing method 有权
标题翻译：印刷掩模，其制造方法和半导体器件制造方法
公开(公告)号：JP2011249567A
公开(公告)日：2011-12-08
申请号：JP2010121446
申请日：2010-05-27
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MASAMITSU , KANEMITSU SHINGO
IPC分类号： H01L21/027 , B29C33/38 , B29C59/02
CPC分类号： H01L21/0274 , B29C59/022 , B82Y10/00 , B82Y40/00 , G03F7/0002 , Y10T428/24479
摘要： PROBLEM TO BE SOLVED: To provide an imprint mask and a manufacturing method therefor enabling accurate positioning, and a semiconductor device manufacturing method.SOLUTION: An imprint mask 1 is composed of a quartz plate 10. On portions of the top face of the quartz plate 10, a plurality of recesses 11 are formed. Portions between the recesses 11 of the quartz plate 10 constitute protrusions 12. On the protrusions 12, namely the portions between the recesses 11, gallium (Ga) is included as impurities. The gallium is introduced by ion injection from the upward direction. Thus, gallium diffusion layers 16 are formed inside the protrusions 12.
摘要翻译：要解决的问题：提供一种能够进行精确定位的压印掩模及其制造方法以及半导体器件制造方法。解决方案：压印掩模1由石英板10组成。在石英板10的顶面的部分上形成有多个凹部11。在石英板10的凹部11之间的部分构成突起12.在突起12上，即凹部11之间的部分，包含镓（Ga）作为杂质。通过向上方向的离子注入引入镓。因此，镓扩散层16形成在突起12的内部。版权所有：（C）2012，JPO＆INPIT

45. 发明专利

JP2010206177A Exposure mask, method for manufacturing same, and method for manufacturing semiconductor device 审中-公开
标题翻译：曝光掩模，其制造方法和制造半导体器件的方法
公开(公告)号：JP2010206177A
公开(公告)日：2010-09-16
申请号：JP2010008005
申请日：2010-01-18
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MASAMITSU
IPC分类号： H01L21/027 , G03F1/22 , G03F1/24 , G03F1/84 , G03F1/86
CPC分类号： G03F1/24 , B82Y10/00 , B82Y40/00 , G03F1/40
摘要： PROBLEM TO BE SOLVED: To provide an exposure mask which can conduct defective inspection with high accuracy, without leakage of light to an area other than an exposure region used as an object for exposure, and to provide a manufacturing method for the mask, and to provide a semiconductor device.
SOLUTION: EUV mask blanks having a light reflecting film 12, a buffer layer 13, and a light-absorbing film 14 formed on an insulating substrate 11 is prepared. In a pattern-forming region 17, the light-absorbing film 14 is selectively removed to form a pattern 18, and the light-absorbing film 14 is removed in a frame-shaped region surrounding the pattern forming region 17. In this frame-shaped region, a buffer layer 13 and a light-reflecting film 12 are then removed to form a light-shielding frame 20. On a substrate 11, a part 15
in a which is arranged inside the light-shielding frame 20 of a laminated film 15 is then connected to a part 15
out , arranged outside the light-shielding frame 20 of the laminated film 15 to form wiring 21. An electron beam is then irradiated and the pattern 18 is inspected. An exposure mask 1 is thereby manufactured.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以高精度地进行缺陷检查的曝光掩模，而不会将光泄漏到除了用作曝光对象的曝光区域以外的区域，并且提供掩模的制造方法并提供半导体器件。解决方案：制备具有形成在绝缘基板11上的光反射膜12，缓冲层13和光吸收膜14的EUV掩模坯料。在图案形成区域17中，选择性地去除光吸收膜14以形成图案18，并且在围绕图案形成区域17的框状区域中去除光吸收膜14。在该框状区域，缓冲层13和光反射膜12然后被去除以形成遮光框架20.在基板11上，将 a中的部分15 布置在遮光罩内然后将叠层膜15的框架20连接到布置在层叠膜15的遮光框架20外侧的部分15 外，形成布线21.然后照射电子束，并且图案 18检查。由此制造曝光掩模1。版权所有（C）2010，JPO＆INPIT

46. 发明专利

JP2009218518A Method of manufacturing semiconductor device, method of managing mask, and method of acquiring exposure amount correction information 审中-公开
标题翻译：制造半导体器件的方法，管理掩模的方法和获取暴露量校正信息的方法
公开(公告)号：JP2009218518A
公开(公告)日：2009-09-24
申请号：JP2008063343
申请日：2008-03-12
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKUHARA KAZUYA , TANAKA SATOSHI , ITO MASAMITSU , INOUE SOICHI
IPC分类号： H01L21/027 , G03F7/20
CPC分类号： G03B27/54 , G03F7/70083 , G03F7/70133 , G03F7/70308
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of increasing precision in resist dimensions on a semiconductor substrate.
SOLUTION: By the method of manufacturing a semiconductor device, light from a light source is transmitted or reflected in a prescribed region on a photomask for emitting to a photoresist on the substrate, thus manufacturing the semiconductor device. The manufacturing method includes: a step of calculating exposure amount correction information, namely distribution on the photomask having intensity of incident light, where intensity of emitted light from the photomask becomes uniform, based on the ratio of emitted light, namely the ratio of intensity of emitted light transmitted or reflected by the photomask to that of incident light at each position in the surface of the photomask; and a step of exposing an exposure region, while correcting intensity of incident light so that a dosage to the irradiation region of the photomask corresponding to the exposure region on the substrate becomes the exposure amount correction information at a corresponding position.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种能够提高半导体衬底的抗蚀剂尺寸精度的半导体器件的制造方法。解决方案：通过制造半导体器件的方法，将光源的光在规定的区域中透射或反射到用于发射到基板上的光致抗蚀剂的光掩模上，从而制造半导体器件。该制造方法包括：基于发射光的比例，即发光的强度比，计算曝光量校正信息的步骤，即具有入射光强度的光掩模的分布，其中来自光掩模的发射光的强度变得均匀由光掩模透射或反射的光在光掩模表面的每个位置处的入射光的发射光; 以及在校正入射光强度的同时暴露曝光区域的步骤，使得对应于基板上的曝光区域的光掩模的照射区域的剂量变为相应位置处的曝光量校正信息。版权所有（C）2009，JPO＆INPIT

47. 发明专利

JP2009122199A Method and device for inspecting mask pattern dimension 有权
标题翻译：用于检查掩模图形尺寸的方法和装置
公开(公告)号：JP2009122199A
公开(公告)日：2009-06-04
申请号：JP2007293580
申请日：2007-11-12
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MASAMITSU
IPC分类号： G03F1/84 , G03F1/86
CPC分类号： G06K9/4604 , G03F1/68 , G03F1/84 , G03F1/86 , G03F7/70625 , G06T7/0006 , G06T7/13 , G06T2207/10056 , G06T2207/30148 , H01L21/67265
摘要： PROBLEM TO BE SOLVED: To provide a method and device for inspecting a mask pattern dimension capable of matching a lithography simulation result and a wafer exposure result at the same degree as a case using pattern contour data directly acquired by an optical method without receiving influence of sidewall shape of a mask pattern. SOLUTION: The method includes: previously obtaining a sidewall shape correction function indicating relationship of a difference of the contour position of two or more pattern contour position data having different thresholds acquired from SEM image data and an optical contour position obtained by the optical method (S1, S2); acquiring the two or more pattern contour position data having the different thresholds from the SEM image data desired to perform lithography simulation (S5); obtaining pseudo optical pattern contour position data from the difference of the contour positions and the sidewall shape correction function (S6); and performing lithography simulation by using the pseudo optical pattern contour position data. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于检查能够匹配光刻模拟结果和晶片曝光结果的掩模图案尺寸的方法和装置，与使用通过光学方法直接获取的图案轮廓数据的情况相同，没有接收掩模图案的侧壁形状的影响。解决方案：该方法包括：预先获得指示从SEM图像数据获取的具有不同阈值的两个或更多个图案轮廓位置数据的轮廓位置的差异与由光学器件获得的光学轮廓位置的关系的侧壁形状校正函数方法（S1，S2）; 从希望进行光刻模拟的SEM图像数据获取具有不同阈值的两个或更多个图案轮廓位置数据（S5）; 根据轮廓位置和侧壁形状校正功能的差异获得伪光学轮廓位置数据（S6）; 以及通过使用伪光学图案轮廓位置数据来执行光刻模拟。版权所有（C）2009，JPO＆INPIT

48. 发明专利

JP2006319350A Substrate treating method 审中-公开
标题翻译：基板处理方法
公开(公告)号：JP2006319350A
公开(公告)日：2006-11-24
申请号：JP2006165029
申请日：2006-06-14
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MASAMITSU , SAKURAI HIDEAKI , YONEDA IKUO
IPC分类号： H01L21/027 , G03F7/30
摘要： PROBLEM TO BE SOLVED: To make the finishing size of a pattern irrespective of fineness of the pattern. SOLUTION: A substrate treating method comprises: a step of a chemical treatment of treating the nearly whole surface of a substrate with a first chemical by continuously discharging the first chemical on the substrate from a first chemical discharge port 261 disposed on the lower surface of a first chemical discharge/suction unit 260, and by continuously sucking a solution on the substrate through two suction mouths 262, 263 disposed so as to interpose the chemical discharge port while the first chemical discharge/suction unit is horizontally and linearly moved relatively to the substrate; and a step of a chemical treatment of the nearly whole surface of the substrate with a second chemical by continuously discharging the second chemical different from the first chemical on the substrate from a second chemical discharge port 271 disposed on the lower surface of a second chemical discharge/suction unit 270, and by continuously sucking a solution on the substrate through two suction mouths 272, 273 disposed so as to interpose the chemical discharge port while the second chemical discharge/suction unit is horizontally and linearly moved relatively to the substrate. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：使图案的精加工尺寸与图案的细度无关。解决方案：一种基板处理方法，包括：化学处理步骤，用第一化学品处理基板的几乎整个表面，通过从设置在下部的第一化学品排出口261上连续排出基板上的第一化学品第一化学品排出/抽吸单元260的表面，并且通过在第一化学品排出/抽吸单元相对于水平和线性地移动而设置成插入化学物质排出口的两个吸入口262,263连续地吸取基底上的溶液到基材; 以及通过将第二化学品的第一化学品与第二化学品不同的第二化学物质连续地从设置在第二化学物质排出口的下表面上的第二化学物质排出口271进行化学处理的基板的几乎整个表面的步骤吸引单元270，并且通过在第二化学品排出/抽吸单元相对于基底水平和线性移动而设置成插入化学物质排出口的两个吸入口272,273连续地吸取基底上的溶液。版权所有（C）2007，JPO＆INPIT

49. 发明专利

JP2006126854A Method for generating mask substrate information 有权
标题翻译：用于生成掩模基板信息的方法
公开(公告)号：JP2006126854A
公开(公告)日：2006-05-18
申请号：JP2005328937
申请日：2005-11-14
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MASAMITSU
IPC分类号： G03F1/38 , G03F1/60 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a method for generating mask substrate information effective for solving the problem of decrease in the yield of products due to degradation of flatness of a mask substrate, caused by chucking of mask substrate on the mask stage of a wafer aligner.
SOLUTION: The main surface of a plurality of mask substrates has a first region where a main pattern is formed and a second region where the substrate is to be chucked on the mask stage of an exposure apparatus. First information, relating to the surface shape of the first region on the main surface of the mask substrate, and second information, relating to the surface shape of the second region of the main surface of the mask substrate are acquired, and the first information and the second information are made to correspond and stored.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于产生掩模基板信息的方法，该掩模基板信息有效地解决了由于掩模基板在掩模台上的夹持而导致的由于掩模基板的平坦度的劣化而导致的产品产量降低的问题晶圆对准器。解决方案：多个掩模基板的主表面具有形成主图案的第一区域和要在基板上被夹持在曝光装置的掩模台上的第二区域。获取关于掩模基板的主表面上的第一区域的表面形状的第一信息以及与掩模基板的主表面的第二区域的表面形状有关的第二信息，并且获取第一信息和使第二信息对应并存储。版权所有（C）2006，JPO＆NCIPI

50. 发明专利

JP2006014292A Image data correction method, lithography simulation method, program and mask 有权
标题翻译：图像数据校正方法，光栅模拟方法，程序和掩码
公开(公告)号：JP2006014292A
公开(公告)日：2006-01-12
申请号：JP2005151063
申请日：2005-05-24
申请人： Toshiba Corp , 株式会社東芝
发明人： ASANO MITSUYO , ITO MASAMITSU , YAMANAKA EIJI , YAMAGUCHI SHINJI
IPC分类号： H04N1/387 , G03F1/84 , G03F1/86 , G06T1/00 , G06T3/00
摘要： PROBLEM TO BE SOLVED: To provide an image data correction method, capable of correcting an image pattern using a small data amount at a high speed and with high accuracy. SOLUTION: The method includes a process (S12) of preparing a correction data for correcting a distortion of the image obtained from an image acquisition section; a process (S22) of acquiring a contour data of a desired pattern obtained from the image acquisition section; and a process (S23) of correcting the contour data of the desired pattern by using the correction data. COPYRIGHT: (C)2006,JPO&NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式