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41. 发明专利

JP2010009646A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2010009646A
公开(公告)日：2010-01-14
申请号：JP2008165012
申请日：2008-06-24
申请人： Toshiba Corp , Toshiba Memory Systems Co Ltd , 東芝メモリシステムズ株式会社 , 株式会社東芝
发明人： UEHARA KAZUTO , WATANABE TOSHIFUMI , ISHIGURO SHIGEFUMI , MURAOKA KAZUYOSHI
IPC分类号： G11C11/413 , G11C11/41 , G11C16/02 , G11C16/04
CPC分类号： G11C7/1027 , G11C7/1006 , G11C7/1039 , G11C11/005 , G11C2029/0411
摘要： PROBLEM TO BE SOLVED: To increase a speed of a clock frequency in a semiconductor memory device configured to perform a clock synchronous burst read operation. SOLUTION: When a buffer memory 21a constituted of one bank is determined as a read target to execute the clock synchronous burst read operation and a start address STADD is a last column address, a burst read control circuit 41 starts counting up a SRAM address MEMADD in a cycle (a first clock) before reaching a read latency cycle (a fourth clock), and latches first read data D3 of a first word to the data latch (A) 281. A row address is switched to start reading of read data D4 of a second word. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提高配置为执行时钟同步突发读取操作的半导体存储器件中的时钟频率的速度。解决方案：当将由一个组成的缓冲存储器21a确定为读取目标以执行时钟同步突发读取操作，并且起始地址STADD是最后一个列地址时，突发读取控制电路41开始计数SRAM 在达到读延迟周期（第四时钟）之前以一个周期（第一时钟）寻址MEMADD，并将第一个字的第一读取数据D3锁存到数据锁存器（A）281。行地址被切换以开始读取读取第二个字的数据D4。版权所有（C）2010，JPO＆INPIT

42. 发明专利

JP4393529B2 Semiconductor device 有权
公开(公告)号：JP4393529B2
公开(公告)日：2010-01-06
申请号：JP2007062620
申请日：2007-03-12
申请人：東芝メモリシステムズ株式会社 , 株式会社東芝
发明人：秀雄加藤 , 徳正原 , 辰也平松 , 栄俊斉藤 , 泰彦本多 , 正男栗山 , 尚史池田
IPC分类号： G11C16/02 , G11C16/06

43. 发明专利

JP2009239005A Semiconductor device and composite lead frame used therefor 有权
标题翻译：半导体器件及其使用的复合引线框架
公开(公告)号：JP2009239005A
公开(公告)日：2009-10-15
申请号：JP2008082944
申请日：2008-03-27
申请人： Toppan Printing Co Ltd , Toshiba Corp , Toshiba Memory Systems Co Ltd , 凸版印刷株式会社 , 東芝メモリシステムズ株式会社 , 株式会社東芝
发明人： OKURA HIROYUKI , ISHIKAWA HISAMITSU , SAEGUSA MASATERU , USHIJIMA TOSHIHIRO , WATABE ATSUSHI , MIYAHARA NORIHIKO , OTA TADAKATSU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/32145 , H01L2224/73265 , H01L2924/19107
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a lead frame and constituted by laminating a plurality of semiconductor elements, the semiconductor device having increased lamination density and also improved functionality by increasing the number of laminated semiconductor elements having characteristics and functions different from each other as the lamination density is increased.
SOLUTION: A first rectangular semiconductor element is provided in a rectangular opening formed on an upper surface of an interposer provided on one surface of the lead frame, and a second rectangular semiconductor element is provided on the other surface side of the lead frame.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种具有引线框并由层叠多个半导体元件构成的半导体器件，该半导体器件具有增加的层叠密度并且还通过增加具有特征和功能的层叠半导体元件的数量来改善功能性当层压密度增加时彼此不同。解决方案：第一矩形半导体元件设置在形成在引线框架的一个表面上的插入件的上表面上的矩形开口中，并且第二矩形半导体元件设置在引线框架的另一表面侧上。版权所有（C）2010，JPO＆INPIT

44. 发明专利

JP2009237602A Memory system 审中-公开
标题翻译：记忆系统
公开(公告)号：JP2009237602A
公开(公告)日：2009-10-15
申请号：JP2008079016
申请日：2008-03-25
申请人： Toshiba Corp , Toshiba Memory Systems Co Ltd , 東芝メモリシステムズ株式会社 , 株式会社東芝
发明人： MIYASHITA TOSHIYUKI , OSHIMA TAKASHI , MURAKAMI TETSUYA
IPC分类号： G06F12/16
摘要： PROBLEM TO BE SOLVED: To provide a memory system improved in operational reliability. SOLUTION: This memory system is provided with: a semiconductor memory 3 with a non-volatile memory cell for storing data; and a backup control circuit 6 for supplying a backup power source 2 and a first external power source (power source C). When the first external power source is interrupted during the write-in of data in the memory cell of the semiconductor memory 3, the backup control circuit 6 supplies a voltage applied from the backup power source 2 to the semiconductor memory 3, and stops the supply of the voltage to be applied from the backup power source 2 after the end of the write-in of the data. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供改进的操作可靠性的存储器系统。解决方案：该存储器系统具有：具有用于存储数据的非易失性存储单元的半导体存储器3; 以及用于提供备用电源2和第一外部电源（电源C）的备用控制电路6。当在半导体存储器3的存储单元中写入数据期间第一外部电源中断时，备用控制电路6将从备用电源2施加的电压提供给半导体存储器3，并停止供应在写入数据结束之后从备用电源2施加的电压。版权所有（C）2010，JPO＆INPIT

45. 发明专利

JP2009211719A Information processing system 有权
标题翻译：信息处理系统
公开(公告)号：JP2009211719A
公开(公告)日：2009-09-17
申请号：JP2009142432
申请日：2009-06-15
申请人： Toshiba Corp , Toshiba Memory Systems Co Ltd , 東芝メモリシステムズ株式会社 , 株式会社東芝
发明人： SAKAGAMI KENJI , TSUNODA HITOSHI , SUKEGAWA HIROSHI
IPC分类号： G06F9/445 , G06F11/10 , G06F12/00 , G06F12/02 , G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a multifunction information processing system applicable to user's use. SOLUTION: A information processing system 60 includes: a multi-value NAND nonvolatile memory 38 which has a plurality of word lines and a plurality of memory cells connected to respective word lines and capable of discriminating N threshold states (N is ≥4), wherein the plurality of memory cells connected to respective word lines form a plurality of addressable pages; and a CPU 50 which can be operated on the basis of program codes stored in the multi-value NAND nonvolatile memory 38. The program codes are stored in only partial pages out of the plurality of pages assigned to respective word lines. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供适用于用户使用的多功能信息处理系统。解决方案：信息处理系统60包括：多值NAND非易失性存储器38，其具有连接到各字线的多个字线和多个存储单元，并且能够识别N个阈值状态（N≥4 ），其中连接到各个字线的所述多个存储器单元形成多个可寻址页面; 以及可以基于存储在多值NAND非易失性存储器38中的程序代码进行操作的CPU 50.程序代码仅被分配给各个字线的多个页面中的部分页面存储。版权所有（C）2009，JPO＆INPIT

46. 发明专利

JP4327626B2 Non-volatile semiconductor memory device 有权
公开(公告)号：JP4327626B2
公开(公告)日：2009-09-09
申请号：JP2004071475
申请日：2004-03-12
申请人：東芝メモリシステムズ株式会社 , 株式会社東芝
发明人：直哉常盤
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/22

47. 发明专利

JP4301749B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP4301749B2
公开(公告)日：2009-07-22
申请号：JP2001225071
申请日：2001-07-25
申请人：東芝メモリシステムズ株式会社 , 株式会社東芝
发明人：栄人坂上 , 聡宮脇 , 清実成毛 , 一仁成田
IPC分类号： H01L21/8247 , H01L21/76 , H01L21/768 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To manufacture a memory cell and a transistor(Tr) of the peripheral circuit of the memory cell in parallel without forming an MOS structure on the surface opposed to an element separation region 107 in the element region of the Tr, with no increase in the pattern area of the Tr. SOLUTION: A tunnel oxide film, a first gate electrode material, and a first CMP stopper material are sequentially formed in the cell region on a silicon substrate. Then, a gate oxide film, a second gate electrode material, and a second CMP stopper material are sequentially formed in the peripheral circuit region on the silicon substrate. AN element region and an element separation region are formed in self-aligned manner on the substrate. An insulating film is formed on the surface of the first gate electrode material in the cell region, and a third gate electrode material is deposited on the surface of the insulating film.

48. 发明专利

JP2009146474A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2009146474A
公开(公告)日：2009-07-02
申请号：JP2007320259
申请日：2007-12-12
申请人： Toshiba Corp , Toshiba Memory Systems Co Ltd , 東芝メモリシステムズ株式会社 , 株式会社東芝
发明人： TOKIWA NAOYA
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C7/1078 , G11C7/109 , G11C16/20
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which can cope with a variation of optimum operation conditions. SOLUTION: The nonvolatile semiconductor memory device has a memory cell array in which electrically re-writable nonvolatile memory cells are arranged, a first register group 9-1 holding control data used for operation control, an adjusting data storing region storing adjusting data for finely adjusting the control data set in the memory cell array, and a second register group 9-2 holding the adjusting data read from the adjusting data storage region. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以应付最佳操作条件变化的非易失性半导体存储器件。解决方案：非易失性半导体存储器件具有其中布置有电可重写非易失性存储器单元的存储单元阵列，保持用于操作控制的控制数据的第一寄存器组9-1，存储调整数据的调整数据存储区域用于精细调整存储单元阵列中的控制数据集，以及保持从调整数据存储区读出的调整数据的第二寄存器组9-2。版权所有（C）2009，JPO＆INPIT

49. 发明专利

JP2009134787A Nand type flash memory 审中-公开
标题翻译： NAND型闪存
公开(公告)号：JP2009134787A
公开(公告)日：2009-06-18
申请号：JP2007308237
申请日：2007-11-29
申请人： Toshiba Corp , Toshiba Memory Systems Co Ltd , 東芝メモリシステムズ株式会社 , 株式会社東芝
发明人： MIYAMOTO JUNICHI , TAKIZAWA MAKOTO , HOSHI SATOSHI , KAWAI TOSHIMASA
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a NAND type flash memory which can reduce an effect of interference between memory cells to data read out from the memory cells. SOLUTION: The NAND type flash memory comprises first memory cells which are connected to a first word line and bit lines and store the data by setting a threshold voltage, second memory cells which are adjacent to the first memory cells, are connected to a second word line and bit lines, and store the data by setting the threshold voltage, and the data is written into after the data is written into the first memory cells, a first sense amplifier circuit connected to the bit lines, and a second sense amplifier circuit connected to the bit lines and the first sense amplifier circuit. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以将存储器单元之间的干扰的影响降低到从存储器单元读出的数据的NAND型闪速存储器。解决方案：NAND型闪存包括连接到第一字线和位线的第一存储器单元，并且通过设置阈值电压存储数据，与第一存储器单元相邻的第二存储器单元连接到第二字线和位线，并且通过设置阈值电压来存储数据，并且在将数据写入第一存储器单元之后写入数据，连接到位线的第一读出放大器电路和第二感测放大器电路连接到位线和第一读出放大器电路。版权所有（C）2009，JPO＆INPIT

50. 发明专利

JP2009094280A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009094280A
公开(公告)日：2009-04-30
申请号：JP2007263405
申请日：2007-10-09
申请人： Toshiba Corp , Toshiba Memory Systems Co Ltd , 東芝メモリシステムズ株式会社 , 株式会社東芝
发明人： UEMURA TERUHIKO
IPC分类号： H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device incorporating a current detecting function.
SOLUTION: The semiconductor device has a conductor pattern 52 which is formed of a wiring layer on a surface of a semiconductor substrate (11) and has a loop shape such that it is connected to the power source of a function circuit 13 in series, a current detecting conductor pattern 54 which is a wiring layer right above the wiring layer forming the conductor pattern 52 and has a shape similar to that of the conductor pattern 52 and is disposed in parallel to the conductor pattern 52, and a bonding pad 13 connected to the current detecting conductor pattern 54.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种结合电流检测功能的半导体器件。解决方案：半导体器件具有由半导体衬底（11）的表面上的布线层形成的导体图案52，并且具有环形形状，使得其连接到功能电路13的电源串联电流检测导体图案54，其是形成导体图案52的布线层正上方的布线层，并且具有与导体图案52的形状相似的形状并且与导体图案52平行设置的接合焊盘 13连接到电流检测导体图案54.版权所有（C）2009，JPO＆INPIT

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