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1. 发明专利

JP2009211719A Information processing system 有权
标题翻译：信息处理系统
公开(公告)号：JP2009211719A
公开(公告)日：2009-09-17
申请号：JP2009142432
申请日：2009-06-15
申请人： Toshiba Corp , Toshiba Memory Systems Co Ltd , 東芝メモリシステムズ株式会社 , 株式会社東芝
发明人： SAKAGAMI KENJI , TSUNODA HITOSHI , SUKEGAWA HIROSHI
IPC分类号： G06F9/445 , G06F11/10 , G06F12/00 , G06F12/02 , G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a multifunction information processing system applicable to user's use. SOLUTION: A information processing system 60 includes: a multi-value NAND nonvolatile memory 38 which has a plurality of word lines and a plurality of memory cells connected to respective word lines and capable of discriminating N threshold states (N is ≥4), wherein the plurality of memory cells connected to respective word lines form a plurality of addressable pages; and a CPU 50 which can be operated on the basis of program codes stored in the multi-value NAND nonvolatile memory 38. The program codes are stored in only partial pages out of the plurality of pages assigned to respective word lines. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供适用于用户使用的多功能信息处理系统。解决方案：信息处理系统60包括：多值NAND非易失性存储器38，其具有连接到各字线的多个字线和多个存储单元，并且能够识别N个阈值状态（N≥4 ），其中连接到各个字线的所述多个存储器单元形成多个可寻址页面; 以及可以基于存储在多值NAND非易失性存储器38中的程序代码进行操作的CPU 50.程序代码仅被分配给各个字线的多个页面中的部分页面存储。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2008071290A Memory controller and host computer 审中-公开
标题翻译：内存控制器和主机计算机
公开(公告)号：JP2008071290A
公开(公告)日：2008-03-27
申请号：JP2006251595
申请日：2006-09-15
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： SAKAGAMI KENJI , TSUNODA HITOSHI , SUKEGAWA HIROSHI
IPC分类号： G06F12/02
摘要： PROBLEM TO BE SOLVED: To provide a memory controller capable of quickly accessing a NAND flash memory even without installing an I/F exclusive to the NAND flash memory or a high-speed SRAM I/F. SOLUTION: A host computer 10 having an SDRAM I/F and a first data buffer and an SDRAM 12 are connected to a system bus 11, and a NAND flash memory 13 is connected to the system bus 11 through a NAND memory controller 20. The memory controller 20 has a second data buffer and transfers invalid data during the transfer of a read burst data block from the NAND flash memory 13 to the host computer 10. The host computer 10 writes valid data transferred from the memory controller 20 in the first data buffer, transfers a write burst data block to the second data buffer to write it and outputs the write burst data block to the system bus 11 in a valid data transfer clock cycle. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种即使没有安装NAND闪存或高速SRAM I / F独有的I / F，也能够快速访问NAND闪存的存储器控制器。解决方案：具有SDRAM I / F和第一数据缓冲器和SDRAM 12的主计算机10连接到系统总线11，NAND闪存13通过NAND存储器控制器连接到系统总线11 存储器控制器20具有第二数据缓冲器，并且在读取突发数据块从NAND快闪存储器13传送到主计算机10期间传送无效数据。主计算机10将从存储器控制器20传送的有效数据写入第一数据缓冲器将写突发数据块传送到第二数据缓冲器以进行写入，并以有效的数据传送时钟周期将写突发数据块输出到系统总线11。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2005275697A Microprocessor boot-up controller, controller for nonvolatile memory and information processing system 有权
标题翻译：微处理器启动控制器，非易失性存储器和信息处理系统控制器
公开(公告)号：JP2005275697A
公开(公告)日：2005-10-06
申请号：JP2004086737
申请日：2004-03-24
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： SAKAGAMI KENJI , TSUNODA HITOSHI , SUKEGAWA HIROSHI
IPC分类号： G06F11/10 , G06F9/00 , G06F9/445 , G06F12/00 , G06F12/02
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： PROBLEM TO BE SOLVED: To shorten average time at system boot-up by permitting SRAM access in a CPU in the shortest period of time by conforming to SRAM ready timing.
SOLUTION: A microprocessor boot-up controller 12 comprises: a volatile memory 24 connected to a nonvolatile memory 38; a selector 36 transferring a boot-up code to the volatile memory 24 from the nonvolatile memory 38; and a controller used for the nonvolatile memory and consisting of a boot-up control sequencer 26 sending CPU reading data to the CPU and forming the CPU in a standby state until completing the transfer of the boot-up code. The microprocessor boot-up controller 12 is connected to an external CPU and the nonvolatile memory 38, and reads the data in the nonvolatile memory 38 to boot-up-control the CPU and is provided with an error detection/correction processing section 40. An information processing system applies the controller 26 used for the nonvolatile memory, the microprocessor boot-up controller 12, and the multiple-valued nonvolatile memory 38.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过允许通过符合SRAM就绪定时在最短时间内对SRAM进行SRAM访问，缩短系统启动时的平均时间。解决方案：微处理器引导控制器12包括：连接到非易失性存储器38的易失性存储器24; 从非易失性存储器38将引导代码传送到易失性存储器24的选择器36; 以及用于非易失性存储器的控制器，包括启动控制定序器26，CPU将CPU读取数据发送到CPU并将CPU形成待机状态，直到完成启动代码的传送。微处理器引导控制器12连接到外部CPU和非易失性存储器38，并且读取非易失性存储器38中的数据以启动CPU并且设置有错误检测/校正处理部分40. 信息处理系统应用用于非易失性存储器的控制器26，微处理器引导控制器12和多值非易失性存储器38.版权所有：（C）2006，JPO＆NCIPI

4. 发明专利

JP2004280790A Ecc control unit 有权
公开(公告)号：JP2004280790A
公开(公告)日：2004-10-07
申请号：JP2004016180
申请日：2004-01-23
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： SAKAGAMI KENJI , SUKEGAWA HIROSHI , TSUNODA HITOSHI
IPC分类号： G06F12/16 , G06F11/10 , H02H3/05
CPC分类号： G06F11/1068
摘要： PROBLEM TO BE SOLVED: To enhance an ECC function by decreasing existing circuit changes in a host or a memory card. SOLUTION: The ECC control unit connected between a host and a memory comprises a fist input/output circuit which inputs/output data in/from the host, a detection circuit which detects, among writing data with a predetermined data length which is inputted to the first input/output circuit, data in a protection region to be protected and a redundant region other than this protection region, a generating circuit which generates an error correction symbol to the data in the protection region, a correction symbol inserting circuit which inserts the correction symbol into the redundant region, and a second input/output circuit which inputs/outputs data in/from the memory. COPYRIGHT: (C)2005,JPO&NCIPI

5. 发明专利

JPS61246997A ELECTRICALLY ERASABLE AND REWRITABLE READ ONLY MEMORY 失效
公开(公告)号：JPS61246997A
公开(公告)日：1986-11-04
申请号：JP8714885
申请日：1985-04-23
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： TSUNODA HITOSHI
IPC分类号： G11C17/00 , G06F12/06 , G11C7/00 , G11C16/02
摘要： PURPOSE:To reduce the number of parts used, to improve reliability and to scale down memory by controlling other blocks in a readable state when a divided memory cell array block is in a write cycle. CONSTITUTION:When a write enable signal inversion WE, a chip enable signal inversion CE and an output enable signal inversion OE come to '0', '0', and '1', respectively the output of the logical gate 21 of a control circuit comes to '1' to cause the output of an AND gate 22 to which an address signal is added to be '1', and an FF 23 is set. Then the enable signal G1 of an Q output and the ready signal RDY1 of an inverse Q signal come to '1' and '0', respectively, and the EEPROM of the 1st block of the divided memory cell array is made in a writable state. Simultaneously the output of an AND gate 24 to which an address signal through an inverter 25 is supplied comes to '0'. The ready signal RDY1 from an FF 26 and an enable signal G2 come to '1' and '0', respectively, and the EEPROM of the 2nd block is made in a readable state. Accordingly the number of memories used and their types in a microcomputer system are reduced, and an increase in reliability and miniaturization an be attained.

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