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31. 发明专利

JPH0936171A INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0936171A
公开(公告)日：1997-02-07
申请号：JP18607095
申请日：1995-07-21
申请人： SANYO ELECTRIC CO
发明人： BABA SEIICHI , SAWADA MINORU , HARADA YASOO
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit device which is lessened in size and enhanced in performance keeping high in high-frequency characteristics. SOLUTION: A microstrip line composed of microstrip conductors 2, dielectric layers 4, and upper grounding conductor layers 6 is provided at prescribed spots on a dielectric board 1, and a wiring layer 7 is formed on a prescribed part of the dielectric layer 4. The wiring layer 7 is electrically insulated from the upper grounding conductor layers 6 and connected to the microstrip conductors 2 through through-holes 5. Bumps 8 are provided at prescribed spots on the wiring layer 7, and semiconductor chips are mounted on the bumps 8 through a flip-chip mounting method.

32. 发明专利

JPH08330517A INTEGRATED CIRCUIT DEVICE AND RESONANT CIRCUIT 失效
公开(公告)号：JPH08330517A
公开(公告)日：1996-12-13
申请号：JP13365095
申请日：1995-05-31
申请人： SANYO ELECTRIC CO
发明人： NISHIDA MASAO , SAWAI TETSUO , HONDA KEIICHI , UDA NAONORI , HIRAI TOSHIKAZU , HARADA YASOO
IPC分类号： H01F27/00 , H01F17/00 , H01G4/40 , H01L21/822 , H01L27/04 , H03H5/02
摘要： PURPOSE: To reduce wiring by decreasing the occupation area of an integrated circuit device using a resonant circuit. CONSTITUTION: An MIM capacitor 20 consisting of a lower metal layer 21, an insulation layer, and an upper metal layer 62 is arranged at the empty region at the center of a spiral inductor 10 consisting of an upper metal layer 61. The edge part inside the upper metal layer 61 of the inductor 10 is connected to the lower metal layer 21 of the capacitor 20 via a contact hole 41 and the edge part outside the upper metal layer 61 of the inductor 10 is connected to a lower metal layer 22 via a contact hole 42. The upper metal layer 62 of the capacitor 20 is connected to the lower metal layer 20 via a contact hole 43.

33. 发明专利

JPH08316745A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH08316745A
公开(公告)日：1996-11-29
申请号：JP12027795
申请日：1995-05-18
申请人： SANYO ELECTRIC CO
发明人： HONDA KEIICHI , KAIZAKI YASUHIRO , HARADA YASOO
IPC分类号： H03F1/52 , H03F3/20 , H04B1/10
摘要： PURPOSE: To provide the amplifier circuit in which a signal level is attenuated without causing a distortion in the characteristic and without destroying post- stage circuits when a signal with an excess level is received. CONSTITUTION: A 1st switch 3 and an attenuator 4 are provided between a 1st RF amplifier 2 and a 2nd RF amplifier 5. A diode switch 7 to detect excess of a prescribed level by a signal level is connected to an input of the 1st RF amplifier 2, and a 2nd switch 8 and a high resistance resistor 9 are provided between the diode switch 7 and a photocoupler 10. A level monitor 15 to detect that the signal level restores a usual level or a very weak level is provided to an output side of the 2nd RF amplifier 5.

34. 发明专利

JPH08316170A ELECTRODE FORMING METHOD 失效
公开(公告)号：JPH08316170A
公开(公告)日：1996-11-29
申请号：JP11576195
申请日：1995-05-15
申请人： SANYO ELECTRIC CO
发明人： INOUE DAIJIRO , HARADA YASOO
IPC分类号： H01L21/28 , H01L21/338 , H01L29/812
摘要： PURPOSE: To provide an electrode forming method enabling the miniaturization with reducing the parasitic capacitance. CONSTITUTION: Opening 3 is formed into a photo resist 2 formed on 7 semiconductor substrate 1 and a first insulation film 4 is formed on the resist 2 and inner face of the opening 3. After removing the film 4 from the side wall of the resist 2, the resist 2 and insulation films 4b and 4c on the resist 2 are removed to form a first trapezoidal insulation film 4a. On the entire face a second insulation film 5 is formed to make the surface even. After etching to expose the upper face of the film 4a, this film is removed to form a trapezoidal hole. A gate metal layer is deposited in the hole and its edge to form a T-shaped gate electrode.

35. 发明专利

JPH08148953A AMPLIFIER AND COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPH08148953A
公开(公告)日：1996-06-07
申请号：JP28230794
申请日：1994-11-16
申请人： SANYO ELECTRIC CO
发明人： SAWAI TETSUO , HONDA KEIICHI , NISHIDA MASAO , UDA NAONORI , HIRAI TOSHIKAZU , HARADA YASOO
IPC分类号： H03G3/30 , H03G3/00 , H04B1/3822 , H04B1/40
摘要： PURPOSE: To provide an amplifier serving for both transmission and reception stably operated in both transmission mode and reception mode with simple circuit constitution by performing feedback from a feedback circuit provided with a feedback resistor whose resistance value is variable and a second active element for the feedback to a first active element for amplification. CONSTITUTION: The feedback from the feedback circuit provided with the feedback resistor R2 whose resistance value is variable and the second active element (FET2) for the feedback is performed to the first active element (FET1) for the amplification. For instance, a resistor is inserted between the drain of the FET1 for the amplification and the gate of the FET2, the feedback is performed by the resistor, gate bias is linked also with a feedback resistor part, a feedback amount is controlled and coping is performed at the time of the reception and at the time of the transmission. That is, at the time of the reception (when the gate bias is deep), the value of the feedback resistor is made large, the feedback amount to the FET1 is reduced and largest possible gain is obtained. At the time of the transmission, the resistance value is made small, the feedback amount is increased and the gain is stabilized small.

36. 发明专利

JPH08148669A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08148669A
公开(公告)日：1996-06-07
申请号：JP28769894
申请日：1994-11-22
申请人： SANYO ELECTRIC CO
发明人： MATSUMURA KOJI , HARADA YASOO
IPC分类号： H01L29/06 , H01L29/12 , H01L29/76 , H01L29/778 , H01L29/788
摘要： PURPOSE: To provide a practical semiconductor device which has a small power consumption and long life, and is capable of high integration and can operate at high speed. CONSTITUTION: An undoped AlGaAs spacer layer 3 having a wide band gap and an N-Al0.22 Ga0.78 As electron supply layer 5 having a wide band gap are made in order on an undoped GaAs buffer layer 2 having a narrow band gap, and an InAs quantum box 4 is provided within the AlGaAs spacer layer 3. The size w1 of the InAs quantum box 4 is approximately 150Å, and the height is approximately 40ÅWhen a specified drain voltage is applied, electrons are accumulated in the InAs quantum box 4 from the channel made in the vicinity of the interface with the AlGaAs spacer layer 3 in the GaAs buffer layer 2. Hereby, even if drain voltage is applied, a drain current ceases to flow practically.

37. 发明专利

JPH08148444A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08148444A
公开(公告)日：1996-06-07
申请号：JP28835594
申请日：1994-11-22
申请人： SANYO ELECTRIC CO
发明人： TERADA SATOSHI , MATSUSHITA SHIGEHARU , FUJII SHIGEYOSHI , HARADA YASOO
IPC分类号： H01L21/28 , H01L21/306 , H01L21/331 , H01L21/338 , H01L29/06 , H01L29/41 , H01L29/47 , H01L29/73 , H01L29/732 , H01L29/812 , H01L29/872
摘要： PURPOSE: To manufacture in self-alignment manner a T-shaped electrode having prescribed configuration and dimention for its head part and leg part in accordance with the position of formation, the width and film thickness of the initial resist pattern and the type of resist material to be used. CONSTITUTION: A SiO2 film 5 and a novolac resist layer 6 are laminated on a wafer having a dummy gate 4 formed by PMMA resist on a semiconductor substrate 1 having a high impurity density layer 2, a part of the novolac resist layer 6 is removed by plasma etching until the SiO2 film 5 on the dummy gate 4 is exposed, the SiO2 film 5 on the dummy gate 4 is selectively removed, and a recessed part 7 is formed. Subsequently, an aperture is formed on a gate electrode pattern by conducting an etching treatment on the dummy gate 4 and the novolac resist layer 6, and a T-shaped gate electrode is manufactured by conducting a metal vapor deposition treatment and a lift-off treatment.

38. 发明专利

JPH0864643A HIGH FREQUENCY INTEGRATED CIRCUIT DEVICE AND HIGH FREQUENCY MEASURING SYSTEM 失效
公开(公告)号：JPH0864643A
公开(公告)日：1996-03-08
申请号：JP19521894
申请日：1994-08-19
申请人： SANYO ELECTRIC CO
发明人： HONDA KEIICHI , HARADA YASOO
IPC分类号： G01R1/06 , H01L21/66 , H03F3/19
摘要： PURPOSE: To obtain a high frequency integrated circuit device and a high frequency measuring system in which highly efficient high frequency measurement is realized inexpensively with high reproducibility. CONSTITUTION: A coupling line 6 is extended substantially perpendicularly to the forward end part of a signal line formed on the rear side at the forward end part of a high frequency probe 1. An input side coupling line 13 and an output side coupling line 14 are formed, respectively, on the opposite sides of an MMIC circuit pattern formed on the circuit board 11 of a high frequency integrated circuit device. At the time of high frequency measurement, the coupling line 6 of the high frequency probe 1 is disposed above the coupling line 6 of the high frequency integrated circuit device while being spaced apart by a predetermined distance therefrom. This structure realizes high frequency coupling of physically separated coupling lines 6, 13.

39. 发明专利

JPH0845963A FORMING METHOD OF MICROPATTERN, GATE ELECTRODE, AND QUANTUM FINE WIRE 失效
公开(公告)号：JPH0845963A
公开(公告)日：1996-02-16
申请号：JP17632894
申请日：1994-07-28
申请人： SANYO ELECTRIC CO
发明人： MATSUSHITA SHIGEHARU , HARADA YASOO
IPC分类号： H01L21/28 , H01L21/306 , H01L21/338 , H01L21/768 , H01L23/522 , H01L29/06 , H01L29/812
摘要： PURPOSE:To provide a method of accurately forming a micro-gate electrode in a short time. CONSTITUTION:A step is formed on a GaAs substrate 1 by SiN film 2 and an SiO2 film 4 is formed covering both the SiN film 2 and the GaAs substrate 1. The SiO2 film 4 deposited on the side wall of the SiN film 2 is selectively removed with very thin buffer hydrofluoric acid solutiomx, whereby a gate opening 6 is provided to the SiO2 film 4 on the GaAs substrate 1 along the side wall of the film 4. A gate metal is formed in the gate opening 6.

40. 发明专利

JPH0832366A BIAS CIRCUIT 失效
公开(公告)号：JPH0832366A
公开(公告)日：1996-02-02
申请号：JP16782094
申请日：1994-07-20
申请人： SANYO ELECTRIC CO
发明人： SAWAI TETSUO , NISHIDA MASAO , UDA NAONORI , HARADA YASOO
IPC分类号： H01P1/00 , H03F3/195 , H03F3/60
摘要： PURPOSE:To obtain the bias circuit whose occupied area is small and which is mounted on a same chip together with a signal processing circuit by forming a drain bias circuit with plural parallel resonance circuits connected in series. CONSTITUTION:A parallel resonance circuit 41 comprising an inductor L4 and a capacitor C8 is connected between a drain of a 1st stage FET 1 and a drain of a 2nd stage FET 2. Parallel resonance circuits 42, 43 of the similar configuration are connected in series with the circuit 41 and the three parallel resonance circuits 41 to 43 form the drain bias circuit, then the bias circuit whose occupied area is small and which is mounted on a same chip together with a signal processing circuit or the like is realized.

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