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1. 发明专利

JPH09321829A TRANSMISSION LINE CHANGEOVER SWITCHING CIRCUIT 失效
公开(公告)号：JPH09321829A
公开(公告)日：1997-12-12
申请号：JP15292196
申请日：1996-05-27
申请人： SANYO ELECTRIC CO
发明人： HIRAI TOSHIKAZU , UDA NAONORI , HONDA KEIICHI , SAWAI TETSUO , HARADA YASOO
IPC分类号： H01P1/15 , H03K17/693 , H04B1/44 , H04L29/14
摘要： PROBLEM TO BE SOLVED: To improve the element separation characteristic between two transmission lines and to make a device using the circuit small. SOLUTION: Field effect transistors(FETs) 1, 4 are conductive and FETs 2, 4 are nonconductive in the case of reception, a reception signal S1 (frequency f1) reaches a reception terminal RX from an input output terminal (RC) to a transmission line 1 and the capacitance of capacitors C1, C3 is set so that a resonance frequency of a bypass circuit (resonance circuit consisting of the FET4, the C1, C3, and a bonding wire L4) to bypass a very small signal S1 given to a transmission line 2 to a ground terminal G is in matching with the frequency f1 of the signal S1 in the case of reception. The conduction of the FETs is inverted in the case of transmission to that of the reception, a transmission signal S2 (frequency f2) reaches the terminal RC from a transmission terminal (TX) via the transmission line 2, and the capacitance of the capacitors C1, C2 is set so that the resonance frequency of a bypass circuit (resonance circuit consisting of the FET3, the C1, C3, and the bonding wire L4) to bypass a very small signal S2 given to the transmission line 1 to the terminal G is in matching with the frequency f2 of a very small signal S2 given to the transmission line 1. As a result, the isolation characteristic between the transmission lines 1, 2 in the case of the transmission and reception is improved.

2. 发明专利

JPH09238059A SWITCH CIRCUIT DEVICE 失效
公开(公告)号：JPH09238059A
公开(公告)日：1997-09-09
申请号：JP4247096
申请日：1996-02-29
申请人： SANYO ELECTRIC CO
发明人： UDA NAONORI , SAWAI TETSUO , HIRAI TOSHIKAZU , HONDA KEIICHI , HARADA YASOO
IPC分类号： H03K17/687 , H03K17/693 , H04B1/48
摘要： PROBLEM TO BE SOLVED: To attain a low voltage operation and high output transmission and to make a device small in size by employing specific multi-gate field effect transistors(FET) for the circuit. SOLUTION: This circuit is provided with multi-gate FETs having n-sets of gate electrodes. Let an internal resistance of a signal source connected thereto and a load resistance be R respectively and a maximum voltage amplitude of transmitted power be Vmax , a pinch-off voltage Vp, a withstanding voltage Vr and a drain saturation current IDSS, of the multi-gate FET satisfy relations of equation |Vp-Vr|>Vmax /(2n) and IDSS>Vmax /(2R). For example, the circuit includes the dual gate FETs 10, 20 and gate resistors R1-R4 formed on a GaAs substrate 100, and the FET10 is connected between terminals A, B and the FET20 is connected between terminals A, C. Then the FET10 sends a signal with a power P1 and has a pinch-off voltage Vp1 and the FET20 sends a signal with a power P2 smaller than the power P1 and has a pinch-off voltage Vp2 shallower than the pinch-off voltage Vp2 .

3. 发明专利

JPH09102542A CONDUCTOR CONNECTING METHOD AND CIRCUIT DEVICE 失效
公开(公告)号：JPH09102542A
公开(公告)日：1997-04-15
申请号：JP26135695
申请日：1995-10-09
申请人： SANYO ELECTRIC CO
发明人： BABA SEIICHI , NAGAMI KIMIHIKO , SAWADA MINORU , HARADA YASOO
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To improve the reliability of interlayer connections between a conductor provided on one insulating resin layer and another conductor provided on another insulating resin layer or between one conductor provided on a substrate and another conductor provided on an insulating resin layer with a connecting conductor which is formed across the upper surface of the uppermost insulating resin layer. SOLUTION: Insulating resin layers 2, 3, 4, and 5 composed of polyimide layers are successively formed on a GaAs substrate 1 and Ti/Au conductor patterns 6, 7, 8, and 9 are respectively provided on the substrate 1 and resin layers 2, 3, and 4 at different positions. The patterns 6 and 7 are electrically connected to each other with a Ti/Au connecting conductor 10 formed through the resin layers 2, 3, 4, and 5, across the upper surface of the layer 5, and through the layers 5, 4, and 3. The patterns 8 and 9 are electrically connected to each other with a Ti/Au connecting conductor formed through the resin layer 5, across the upper surface of the layer 5, and through the layers 5 and 4. Therefore, a connecting method by which highly reliable interlayer connections can be obtained can be realized.

4. 发明专利

JPH0951004A SEMICONDUCTOR DEVICE AND FABRICATION OF THE SAME 失效
公开(公告)号：JPH0951004A
公开(公告)日：1997-02-18
申请号：JP19950695
申请日：1995-08-04
申请人： SANYO ELECTRIC CO
发明人： FUJII SHIGEYOSHI , MATSUSHITA SHIGEHARU , SAWADA MINORU , HARADA YASOO
IPC分类号： H01L29/41 , H01L21/302 , H01L21/3065 , H01L21/318 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has prevented deterioration of characteristics due to damage in the channel region occurring when a protec tion film on a high conductive region. SOLUTION: Difference ((Wgp-L) between the length Wgp of the umbrella part of a T type gate electrode 7a in the channel direction is set to 0.6μm or more but is 2.0μm or less and more preferably to 1.0μm or more but is 2.0μm or less. Thereby, damage by etching on the channel region between the high conductive regions 5a, 5b can be prevented and increase of source resistance can be controlled.

5. 发明专利

JPH0923192A LIGHT MODULATOR AND OPTICAL FIBER COMMUNICATION SYSTEM 失效
公开(公告)号：JPH0923192A
公开(公告)日：1997-01-21
申请号：JP16944195
申请日：1995-07-05
申请人： SANYO ELECTRIC CO
发明人： BABA SEIICHI , SAWADA MINORU , HARADA YASOO
IPC分类号： H04B10/516 , G02F1/03 , H04B10/2507 , H04B10/2575 , H04B10/54 , H04B10/61 , H04B10/152 , H04B10/04 , H04B10/06 , H04B10/142
摘要： PROBLEM TO BE SOLVED: To provide a light modulator and an optical fiber communication system capable of suppressing a relative strength noise and improving an SN ratio. SOLUTION: A light distributor 11 equally distributes a light carrier A to 1st and 2nd light carriers A1, A2. An 180 deg. distributer 12 distributes an RF subcarrier signal B to 1st and 2nd RF subcarrier signals B1, B2 of which phases are unutuaily inverted by 180 deg.. An electro-optical modulator 13 modulates the 1st optical carrier A1 by the 1st RF subcarrier signal B1 and outputs a 1st optical signal C1. An electro-optical modulator 14 modulates the 2nd optical siganal A2 by the 2nd RF subcarrier signal B2 and outputs a 2nd optical signal C2. Photodiodes 6, 7 respectively convert the 1st and 2nd optical signals C1, C2 transmitted through optical fibers 4, 5 into 1st and 2nd electric signals D1, D2. An 180 deg. synthesizer 8 inverts the phase of the signal D1 by 180 deg. and synthesizes the inverted signal and the 2nd electric signal D2.

6. 发明专利

JPH08250517A SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPH08250517A
公开(公告)日：1996-09-27
申请号：JP5072295
申请日：1995-03-10
申请人： SANYO ELECTRIC CO
发明人： INOUE DAIJIRO , MATSUSHITA SHIGEHARU , MATSUMURA KOJI , SAWADA MINORU , HARADA YASOO
IPC分类号： H01L29/812 , H01L21/338 , H01L29/778
摘要： PURPOSE: To enable high doping concentration of a first impurity element and restrain deactivation of impurities by heat treatment by laminating a second epitaxial growth layer doped with a second impurity element in a first epitaxial growth layer doped with a first impurity element. CONSTITUTION: A GaAs buffer layer 2, a p-type GaAs layer 3, an n-type GaAs channel layer 4 and a P-type GaAs layer 5 are formed on a semi-insulating GaAs board 1 one by one by epitaxial growth. Therefore, even if the channel layer 4 is doped with high concentration Si, strain in the channel layer 4 is compensated by the p-type GaAs layers 3, 5 and relaxed. Therefore, even if heat treatment during formation of high conduction region 9a, 9b and heat treatment for obtaining ohmic contact of a source electrode 7 and a drain electrode 8 are carried out, carrier in the channel layer 4 is not deactivated.

7. 发明专利

JPH08129426A NEGATIVE VOLTAGE CONTROL CIRCUIT 失效
公开(公告)号：JPH08129426A
公开(公告)日：1996-05-21
申请号：JP26667694
申请日：1994-10-31
申请人： SANYO ELECTRIC CO
发明人： NISHIDA MASAO , SAWAI TETSUO , HONDA KEIICHI , KAIZAKI YASUHIRO , UDA NAONORI , HIRAI TOSHIKAZU , HARADA YASOO
IPC分类号： G05F1/56
摘要： PURPOSE: To accurately output a desired negative voltage through an output node by setting the resistrance division ratio calculated by a 2nd resistance division means at the value equal to that calculated by a 1st resistance division means. CONSTITUTION: An E-FET 10 is connected between a division point n1 set between the resistances R1 and R2 and an output node 40, and the gate of the E-FET 10 is connected to a division point n2 set between the resistances R1' and R2'. The value of resistances R1, R2, R1' and R2' are referred to as R1, R2, R1' and R2' respectively and then set as R1:R2= R1':R2'. Then, the voltage of both points n1 and n2 are set at V1 and V2 respectively, and the negative voltage -VN is set at -2V. When the control voltage IN is 0V, V1=V2 is satisfied. Therefore, the E-FET 10 is turned off and no output voltage is acquired at the node 40. When the voltage IN is set at 3V, V1

8. 发明专利

JPH0878678A FIELD EFFECT TRANSISTOR 失效
公开(公告)号：JPH0878678A
公开(公告)日：1996-03-22
申请号：JP21407094
申请日：1994-09-07
申请人： SANYO ELECTRIC CO
发明人： UDA NAONORI , SAWAI TETSUO , NISHIDA MASAO , HIRAI TOSHIKAZU , HARADA YASOO
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52 , H01L29/78
摘要： PURPOSE: To break the coupling by the voltage between a source electrode and a drain electrode which are made each in comb shape and are combined, with comb-toothed electrodes on one side of one electrode arranged in the gaps among the comb-toothed electrodes on the other side of the other electrode. CONSTITUTION: The distance between each tip of the comb-toothed electrode parts 1b of a source electrode 1 and each inmost recess of the gaps 2c of a drain electrode 2 wherein it is positioned and the distance between each tip of the comb-toothed electrode parts 2b of the drain electrode 2 and each inmost recess of the gaps 1c of the source electrode 1 wherein this is positioned are made 20μm or over each.

9. 发明专利

JPH0851134A METHOD FOR DETERMINING EQUIVALENT CIRCUIT OF PACKAGE 失效
公开(公告)号：JPH0851134A
公开(公告)日：1996-02-20
申请号：JP18461994
申请日：1994-08-05
申请人： SANYO ELECTRIC CO
发明人： UDA NAONORI , SAWAI TETSUO , NISHIDA MASAO , KAIZAKI YASUHIRO , HIRAI TOSHIKAZU , HARADA YASOO
IPC分类号： G01R31/26 , G06F17/50 , H01L21/66
摘要： PURPOSE:To easily and accurately determine the equivalent circuit of a package of an arbitrary shape. CONSTITUTION:A package is divided into a first basic shape 100 including one lead pin, a second basic shape 200 for obtaining the mutual action between the pin and a die pad and a third basic shape 300 for obtaining the mutual action between the adjacent pins, and the S parameter of the shapes are obtained by electromagnetic field simulation. The circuit constant of an equivalent circuit corresponding to the first shape is obtained by fitting the S parameter. The already obtained constant is fixed, and the circuit constants of the equivalents corresponding to the second and third shapes are sequentially obtained by fitting the S parameter. Eventually, the constants are combined to determine the complete equivalent circuit of the package.

10. 发明专利

JPH0778837A FIELD-EFFECT TRANSISTOR 失效
公开(公告)号：JPH0778837A
公开(公告)日：1995-03-20
申请号：JP24868293
申请日：1993-09-08
申请人： SANYO ELECTRIC CO
发明人： NOGAWA KAORU , NISHIKAWA MADOKA , YAMADA SETSU , HARADA YASOO
IPC分类号： H01L21/338 , H01L29/812
摘要： PURPOSE:To provide the semiconductor device wherein the fluctuation in the Vp characteristics by heat treatment is suppressed. CONSTITUTION:An n type active layer 3 as well as n type source 4 and drain 5 holding the active layer 3 are formed on a substrate 1. Besides, a protective film 2 is deposited on the substrate 1. At this time, a source electrode 6 and a drain electrode 7 as ohmic electrodes are respectively formed on the source 4 and the drain 5 through the intermediary of the holes through the protective film 2 while a gate electrode 8 as a Schottky electrode is formed on the active layer 3 also through the intermediary of the other hole bored through the protective film 2. On the other hand, the first layer 8a as a part in contact with the active layer 3 of the gate electrode 8 is formed of a Schottky metal containing sulfur while the second layer 8b comprising Al etc., is deposited on the first layer 8a.

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